ProDesign unveils CHIPit Gold Edition Pro, a new high-speed prototyping platform

Second Generation of High Speed ASIC Verification Platform Designed for Multimedia Applications

SAN JOSE, CALIF., February 21, 2005 -ProDesign USA, a leading supplier of high-speed ASIC and SoC verification platforms, today announced the immediate availability of CHIPit Gold Edition Pro. The first public demonstrations of the new platform will be at DATE 2005 (Munich, March 7-9, booth E4100).

ProDesign’s new high-speed prototyping platform is cost effective, flexible and based on innovative methodologies that make it applicable wherever functional ASIC design verification is required. Uses range from the initial phases of design algorithm creation, through the basic IP development and debugging, to the validation of complex SoC designs and early “quasi prototyping” for firmware and software development.

CHIPit Gold Edition Pro specifically targets multimedia ASIC and SoC designers and features important functions such as multi-gigabit serial links, embedded PowerPC processors, SSRAM & DDR-RAM memories and PCI Express, LVDS, USB 2.0 and DVI interfaces.

“Many of our CHIPit customers are designers of multimedia applications who put a high value on the speed at which they can run their ASIC verification,” stated Joseph Rothman, CEO of ProDesign USA. “Our Gold Edition Pro keeps pace with the needs of these customers, allowing a system speed over 200 MHz, and on top of that features the newest interfaces. We also attached great importance to the comprehensive software package that is included. Our very easy to use system now also offers a variety of ASIC design importing and debugging options.”
CHIPit Gold Edition Pro is a standalone system that communicates with the host via the patented, very high speed ProDesign 528 Mbit UMRBus Communication System or via a 100 Mbit Ethernet interface. The system supports the newest interfaces such as USB 2.0, DVI Input and Output, LVDS and PCI Express. By using UMRBus technology, multiple independent communication channels between the host and design can be set up that allow for interaction with the ASIC. The designer can choose between a C/C++ and a Tcl/Tk programming interface and has the option to store and load the configuration data with an integrated SD card interface.

CHIPit Gold Edition Pro uses two Xilinx Virtex-II Pro XC2VP70/100 devices in the largest pin count package, offering multi-gigabit serial links, embedded PowerPC processors and 744 user I/Os on 6 extension sites. The new CHIPit system also supports 2 x 512kx36 SSRAM and 4 x 32Mx32 DDR-SDRAM onboard memories. Onboard temperature monitoring and built-in self-test guarantee that the ASIC design is running on known-good hardware.
The Software Package

CHIPit Gold Edition Pro comes with a comprehensive software package including CHIPit Manager, Visibility Tool, HDL Bridge and Signal Tracker. The CHIPit Manager for complete project administration and system configuration supports design implementation (synthesis/place and route) and handles design partitioning on the prototyping system. The Visibility Tool eases debugging of the design by executing the internal design signals after synthesis/place and route, which can then be analyzed with tools such as logic analyzers.

Other highlights for debugging are ‘HDL Bridge’ and ‘Signal Tracker’. HDL Bridge is a powerful tool that provides a direct link between a simulation environment (RTL or gate level) and a partial or whole DUT (design under test) that is loaded in the CHIPit system. This ensures that the entire design or parts of it run in hardware already in the simulation phase. Combined with Signal Tracker for visualization of the internal signals in the simulator, the designer is provided with an ideal solution for rapid design debugging.

Pricing and Availability
The CHIPit Gold Edition Pro is available from March 30, 2005 with U.S. pricing starting at $29,000 and European pricing starting at €23,000.