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Optimize your DSPs for power and performance
By Michel Laurence, Octasic
January 04, 2007 -- dspdesignline.com
The ever-growing demand for rich, multimedia signal processing in mobile devices raises a chronic technology challenge. The challenge is to squeeze higher functionality and performance within increasingly tighter power and space constraints. As a result, power-performance metrics are now a central concern in DSP design. New methods have been devised enabling designers to address the main areas of power consumption-- namely leakage power, clock trees, logic transitions, and power grids-- to significantly improve performance compared to conventional techniques.
In today's CMOS technology, power is consumed in two basic ways: statically and dynamically. Static power is consumed continuously--even during standby operation--through various leakage mechanisms. Dynamic power is consumed only during activity, such as logic and interface operations.
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