Embedded DSP Software Design on a Multicore SoC Architecture: Part 1

The hardware architecture of an embedded media SoC

By Robert Oshana, Texas Instruments
November 21, 2007-- dspdesignline.com

Designing and building embedded systems is a difficult task, given the inherent scarcity of resources in embedded systems (processing power, memory, throughput, battery life, and cost). Various trade-offs are made between these resources when designing an embedded system.

Modern embedded systems are using devices with multiple processing units manufactured on a single chip, creating a sort of multicore system-on-a-chip (SoC) can increase the processing power and throughput of the system while at the same time increasing the battery life and reducing the overall cost.

One example of a DSP based SoC is shown in Figure 11.1 below. Multicore approaches keep hardware design in the low frequency range (each individual processor can run at a lower speed, which reduces overall power consumption as well as heat generation), offering significant price, performance, and flexibility (in software design and partitioning) over higher speed single-core designs.

Figure 11.1. Block diagram of a DSP SoC

There are several characteristics of SoC that we will discuss [1]. I will use an example processor to demonstrate these characteristics and how they are deployed in an existing SoC.

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