Designing FPGA Based Reliable Systems Using Virtex-5 System Monitor
Sanjay Kulkarni, XilinxNeed of Reliable System Monitoring
The ever changing technology has made the world as a global village, where every part of the globe is connected with the rest through either wireless systems or physical network. The fast track development and 24x7 operations have put tremendous pressure on the servers, networking systems and communication equipments. It has become necessary that these systems should operate reliably irrespective of the change in external operating environment like the temperature, humidity, and power fluctuations or, on chip conditions like on-chip temperature, internal voltage levels etc. Measuring the reliability of these physical systems is must for every operational unit. The intelligent hardware monitoring systems usually monitor server operations as well as communication systems physical health characteristics, such as temperature, voltage, fans, and power supplies etc which are analog in nature.Components of Reliable Monitoring Systems
An ideal component of any hardware monitoring systems is a Microcontroller (Micro Controller Unit) with a high I/O count, multiple interface standards, and an analog interface. The need of high I/O count, to monitor multiple status lines, drive bays, CPU cards, etc. poses problems for the standard 8-bit MCU. Another limitation of using the conventional microcontroller system is that the on-chip temperature/voltage measurement is not possible.Role of FPGA in System Monitoring
FPGAs, having a large pin count with support for multiple I/O standards, will be an advantage in system monitoring kind of applications. By adding some basic analog I/O and on-chip transducers to the FPGA, it can also be configured to monitor its on chip environment parameters and pass this information to the host computer along with other information concerning external power supply and thermal conditions. The continuous monitoring of various transducer inputs can be managed by using either a soft micro processor core (MicroBlazeTM
), or a simple state machine. This would off load the parent system or the host computer. When the monitored parameters, violate the normal operating range then only the host computer will be interrupted. Its a well know fact that avoidance is one of the key parameters of highly reliable systems. Avoidance means taking the corrective actions like triggering the FPGA or/and the complete system to go in to power down mode, interrupting the host processor. This helps in taking the corrective actions at the system level or a technician call out is made to resolve the adverse situation.System Monitor Value Propositions
One of the examples of using Virtex-5 FPGA, along with system monitor, is in the Intrusion Detection System (IDS). An intrusion detection system inspects all inbound and outbound network activity and identifies suspicious patterns that may indicate a network or system attack from someone attempting to break into or compromise a system. Traditional processing architectures cant meet the challenges like increasing the number of applications requiring security, the proliferation and ever-greater sophistication of rogue traffic, and the widespread dependence on networks to handle every aspect of an organization's operations, high-speed protocols such as Gigabit Ethernet. The Virtex-5 FPGAs not only can do the job, but they also offer an unmatched combination of low cost, tremendous flexibility, and ease of use. The on-chip system monitoring capability has replaced the need of having separate hardware monitoring equipments. Along with handling the network traffic, the Virtex-5 FPGA system monitor performs tasks like on chip temperature & voltage measurement, thermal management of the complete system, monitoring the systems power supply state and generating alarms.Figure 1 : Virtex-5 System Monitor (SYSMON Hard Macro) Block DiagramHow Virtex-5 Helps in System Monitoring?
The Xilinx Virtex-5 series of FPGA provides the System Monitoring capability by having SYSMON hard macro located at the center of FPGA. The Virtex-5 SYSMON hard macro function (block diagram as shown in Figure 1) is built around a 10-bit, 200-kSPS (kilo-Samples Per Second) Analog-to-Digital Converter (ADC) with a resolution of 1 mV. When combined with a number of on-chip sensors, the ADC is used to measure FPGA physical operating parameters like on-chip power supply voltages and die temperatures. The ADC produces a full-scale 10-bit code (3FFh) with 1V differential input voltage on its external analog inputs. Access to external voltages is provided through a dedicated analog differential-input pair (VP/VN) and 16 user-selectable analog inputs, known as auxiliary analog inputs (VAUXP [15:0], VAUXN [15:0]). The external analog inputs allow the ADC to monitor the physical environment of the board, or enclosure. The dedicated analog inputs and the auxiliary analog inputs can be driven either single ended or as truly differential sources.
Initialization of System Monitor In the Virtex-5 Based System
The SYSMON hard macro is instantiated in the user system and configured via a number of Configuration Registers. These registers typically control the different operating modes of SYSMON hard macro which are given here,
- Calibration Coefficients to the ADC
- Single Channel Event Triggering Mode
- Single Channel Continuous Cycling Mode
- Continuous Cycling Mode
- Power Down Mode
- Sampling Frequency of internal ADC
- Averaging the on-chip parameter measurements
The SYSMON hard macro ensures accuracy over environmental conditions and time, if auto calibration is enabled. Automatic calibration and self check features ensure accurate and reliable measurements over a temperature range of -40°C to +125°C.
If only a single channel is to be monitored then the SYSMON can be configured in the Single Channel Event Driven Mode or Single Channel Continuous Cycling Mode. The Single Channel Event Driven Mode can be controlled internally by providing an active high pulse to internal conversion start signal, or externally by providing a single clock wide active high pulse on CONVST input pin. When the need of monitoring all or some of the 17 analog channels arises then the SYSMON should be configured in Continuous Cycling Mode. The sequence of the channels to be monitored can be set by configuring the Sequence Register of the SYSMON hard macro. How to Configure Virtex-5 SYSMON Hard Macro?Figure 2 : System Monitoring Using Virtex -5 Fpga
A register-file-based (128 16-bit registers) interface through JTAG TAP or fabric allows easy access to the measured data and the SYSMON hard macro Control Registers. The SYSMON hard macro provides user programmable alarm thresholds (upper and lower limits) for the various on-chip sensors like on chip temperature, VCCaux, Vccint etc. These threshold values can be provided by configuring the Threshold Registers in the SYSMON hard macro. Thus, if any of the on-chip monitored parameters move outside of the user-specified operating range, the related alarm output becomes active. The alarm signals of the SYSMON hard macro can be connected to the system interrupt pins to raise the alarm for any critical situation. These alarms are automatically deactivated when the measured parameters fall in the assigned range. The power down mode is optional and can be activated if the FPGA on-chip temperature goes above 125°C by initializing a special alarm called as Over Temperature (OT). The over-temperature signal is deactivated when the device temperature falls below a userspecified lower limit. The measured values for both on-chip sensors and external channels are read after completion of the ADC conversion. The Status Registers store the maximum and minimum measurements for each of the on-chip sensors.
All SYSMON hard macro features are customizable at run time through the Dynamic Reconfiguration Port (DRP) and the SYSMON hard macro Configuration Registers (Control Registers). The access to the DRP is either through the external JTAG TAP port, or through the soft IP like XPS Sysmon ADC, which is available in latest EDK toolkit (EDK 8.2i onwards). The JTAG interface can be provided either through the ISE tool (ISE 8.2i onwards) (as shown in Figure 3), or with a simple TCL script which runs on the XMD command prompt. The JTAG interface provides full Read/Write access to the SYSMON hard macro register file interface. After power-up, the SYSMON hard macro operates in the safe mode and its functionality can be customized, if required, through the JTAG TAP. These control registers can also be initializable at design time when SYSMON hard macro is instantiated in a design. The external access to the register file based interface through JTAG TAP can be monitored by referring the status of JTAG specific signals from SYSMON hard macro. The SYSMON arbiter allows either JTAG access or the DRP access using soft IP at a given time.Configuring the Virtex TM -5 SYSMON using Xilinx ISE Tools
The Xilinx ISE (ISE 8.2i onwards) tool provides a direct method to configure the SYSMON in the desired mode for any particular application with out going through the above mentioned method. The SYSMON hard macro can be initialized in the user design by using the IP Coregen & Architecture Wizard option from the New Source Wizard sub-menu of Project menu option in the ISE tool. The System Monitor Wizard v1.0 can be found in the FPGA Features and Design option. The System Monitor Wizard (as shown in Figure 3) is the most effective tool to configure the required set of registers, channels, different operating modes and the sequence of the channels, threshold values ofFigure 3 : Configuration of SYSMON Using System Monitor Wizard in Xilinx ISE Tools
registers, setting up the alarms, ADC calibration, inclusion/exclusion of DRP, CONVST, external analog inputs etc. At the end of configuration the wizard will generate the HDL source which is effectively a part of the system, which uses the SYSMON functionality.How Chip Scope Tool Helps in SYSMON Parameter Monitoring?
Xilinx Chip Scope tool (ISE 8.2i onwards) is capable of providing a GUI interface with the SYSMON hard macro. It communicates with the SYSMON macro through the JTAG interface when the FPGA is powered up. This option of SYSMON configuration and monitoring is used even before the FPGA is configured. It automatically detects the presence of SYSMON on the JTAG chain and allows user to display the measurement data. User can modify the Configurable Registers, Sequence Registers and the Threshold Registers through GUI any time during the course. The tool allows setting the depth and the window of the measured parameters. User can save the measured data along with the time stamp in a log file for separate analysis. Refer Figure 4 for more information.Figure 4 : Monitoring Voltage, Temperature, Current via the JTAG interface and Chip Scope Tool
To achieve the best possible performance and accuracy with all measurements (both on-chip and external), six dedicated pins are provided for the ADC reference and power supply (refer Figure 5 for dedicated pins). Care must be taken with the connection of these pins to ensure the best possible performance from the ADC. For typical usage, the reference voltage between VREFP and VREFN should be maintained at 2.5V ± 0.2% using an external reference IC.Disabling the Virtex-5 System Monitor:
The choice of inclusion of the SYSMON hard macro in the Virtex-5 based systems is optional. The SYSMON hard macro operates even though it
has not been instantiated in a design as well as prior to the FPGA configuration. This default operating mode allows the SYSMON hard macro to measure onchip temperature and voltages only. If not used in the system, the SYSMON hard macro should be disabled to save the power consumption. The SYSMON hard macro can be permanently disabled, by connecting its dedicated supplies and input pins to ground (as shown in Figure 5).Figure 5 : Disabling the Virtex-5 FPGA System Monitor FunctionConclusion:
The system monitoring capability has added extra benefits while using the FPGA based systems. It is possible to use the SYSMON hard macro as a dedicated general-purpose ADC in an application by disabling the monitoring of the on-chip sensors. The basic System Monitor functionality can also be extended by the processor to include custom functionality and support various communication protocols for system management or monitoring (e.g., Ethernet, UART, and I2C). The reliable monitoring systems can be implemented efficiently with Virtex-5 series FPGA. To design the FPGA based systems, the choice of Virtex-5 would be appropriate, as in addition to its own technological and functional advantages, Virtex-5 FPGA adds the capability of monitoring (and taking corrective actions like enabling the FPGA to go in power down mode etc) the systems health.References:
Virtex-5 System Monitor User Guide, UG192
XPS Sysmon ADC IP Core (v1.00.a) (DS620)About the Author:
Member of Processor IP development Team in Xilinx India Technology Services Pvt. Ltd., Hyderabad, India
Contact Xilinx, Inc.