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Tips on using CPLDs to reduce system processor power consumption
Embedded.com -- (05/26/08, 01:00:00 AM EDT) One of the most critical factors in designing portable electronics today is reducing overall system power consumption. With increased consumer expectations, portable devices require longer battery life and higher performance. Even power reductions on the order of 10mW are crucial to portable system designers and manufacturers. Designers use several design techniques to significantly reduce overall system power consumption, such as:
Many manufacturers today offer devices with power saving modes that temporarily suspend the device from its normal operation. These devices have the option to power down or transition to a non-functioning state if the device is not active for a specific amount of time. This feature is available on many of today's microprocessors and MCUs. By taking advantage and managing the operating mode of large power consumers on a PCB, such as the processor, the overall power consumption of the system can be reduced significantly. Reducing power consumption involves correct management of the operating mode of a device and designing a system to take advantage of the modes a device can operate within. Offloading operations of the microprocessor allows it to stay in its low-power state for a longer amount of time. One way to reduce system power is to allow a low-power PLD, such as a CPLD, to manage these offloaded operations. This article describes this possibility, along with types of operations that allow a processor to remain in a low-power state longer, thereby reducing system power consumption.
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