Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 2
By Scott Schaefer, Micron TechnologyEmbedded.com (11/25/08, 03:40:00 PM EST)DDR2/DDR3 Functionality
Up to this point, the discussion started in Part 1 has focused on clock jitter in terms of a DRAM's functionality as opposed to it working correctly; there is a subtle but important difference. DDR2/DDR3 clock jitter specifications are applied to input timings only; output timings are stated without any clock jitter and any clock jitter effects must be added to them.
Suffice it to say that there is a reasonably good explanation why this became the industry-standard methodology. Thus, clock jitter analysis needs to be separated between input timings concerns (will the device function correctly?) and output timing concerns (will the data eye be big enough?)
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