Sean Dart, President and CEO of Forte Design Systems Inc.
EETimes (2/4/2011 10:53 AM EST)
The future is high-level synthesis (HLS). As a developer of HLS software, Fortes vision for this methodology is far reaching and all inclusive, and one weve considered for some time. We share a common belief with other HLS developers that it will replace the register transfer level (RTL) as the predominant front-end design methodology and will be used to do everything logic synthesis can do today.
The semiconductor industry is not there yet, and getting to that point will clearly take time, both in terms of extending the capabilities of the technology and driving adoption by the design community, but the trend is clear. The transition from gate-level design to RTL set a clear precedent. The industry saw the adoption of new tools, development of designs and intellectual property (IP) and, eventually, the bulk of designs and IP exist in the form of RTL code.
A number of key drivers and requirements enable such a methodology transition, beginning with productivity. Productivity is increased through the delivery of a more abstract design language. Back in the day, when hardware designers transitioned from assembly code to high-level languages for software development, they saw a huge increase in productivity, delivered by abstraction. Coders could add significantly more functionality with less lines of code; debugging was easier; maintenance was easier; code was more understandable; and reuse was increased.
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