Analog IP Nirvana: a modular based design methodology for addressing the agility
Sanjeev Sharma, Stixis
Massive investment in process node by various foundries  and IDMs has brought lots of opportunities in System on Chip (SOC) design. Every 2 years, a new node has been introduced by foundries that have resulted 50% shrinkage in chip area. With passing time, the SOC complexity has increased and more logic per unit area has been integrated. From business realization, it is important to develop SOC which meets the Time to market and other technical specifications. Analog and RF circuit which constitutes almost 10% of SOC area possesses largest threat for SOC failure and schedule variance. It is important to have a design methodology which address the both issues and provide seamless integration of analog and RF circuits with digital counterpart. In this paper we propose a modular design methodology which can handle the agility of analog IP and help to achieve the first pass silicon. A case on PLL design will be discussed to highlight the key benefit of this design methodology.
It is evident that the current digital design methodology is smart enough to adapt the process change and most of the fab-less and IDM are able to migrate as per the process node change, which has resulted larger integration and more logic per mm2 of die area. Due to inherent challenges with the analog and RF design (ARF), these companies skip 5-6 years time for next migration from analog IP perspective. Many companies for example ARM, IBM etc put special emphasis on the smarter systems which are high performance and low power systems. Energy efficiency is the fundamental principle for these smart systems. In last one decade we have seen that battery powered handheld devices brought lots of innovation in technology market. Now the internet enabled handheld devices will be the key driver of next decade and so. This means the SOC needs to be fast and power efficient and
hence the analog and RF circuits need to address the power and performance issue simultaneously.
GIA has predicted that the SOC market will cross US$39.5 Billion by 2015 and average development cost of SOC will increase nearly 40% on migrating from 32nm to 28nm and nearly 30% on migrating from 28nm to 22nm.
Figure 1 : IC design cost at different process node (source JRC, 2009)
Most of the IP design services companies invested heavily in the analog IP program which can be integrated seamlessly with the digital circuits. But due to rapid change in process node and poor ROI, they were not able to catch the pace of the digital design. Today the analog IP market needs highly flexible analog IP macros that can be integrated in roadmap technologies without risking the SOC. From design methodology perspective, the analog design methodology needs to adapt to the change in requirements due to influencing factors like process change, spec improvisation or even change in marketing input. Unfortunately the design cycles required for implementation of analog and RF design are relatively more compare to digital flow. Recently, the non availability of analog and RF designers have put analog IP development on back foot. In recent past many authors have discussed the SOC challenges  and also proposed some good solutions to address these challenges. Unfortunately the traditional design flow was not adequate to adapt these solutions to satisfactory level. We are proposing a highly modular and flexible design methodology to address the agility of analog IP requirement. A robust verification methodology has been proposed to minimize the risk of silicon failure.
Often change in requirement specifications and variance in process technology parameters put tremendous pressure on design cycle of analog IP. Lack of flexibility often results in redesigning the IP every time whenever there is change in specification. It is also seen that many designers need significant time to identify the right architecture which may meet the design goal. Lack of automation of verification can lead to improper coverage of circuit verification across the PVT. For complex circuits like PLL, the simulation time plays critical role and leads to insufficient coverage of verification.
Figure 2: Modified Design Methodology
The design methodology as per Figure 2 , addresses some of the key challenges mentioned above. For complex SOC, the manual optimization of analog circuits is time consuming. We have seen that the equation based optimizer  or model based optimizer  plays important role in architecture decision. Use of accurate Verilog AMS models or Matlab models improves the productivity and helps designer to decide on the right architecture. Few of the commercial model based or equation based optimizers are capable enough to produce proven schematic which can meet the design goals. Recently equation based optimizers have been used to improve overall yield. The concept of using these model based tool flow along with the tradition flow will help to improve the productivity and also optimize the circuit as per the objective without spending longer design cycle. These tools are also useful in fixing up the post LPE issues or Monte Carlo yield issues.
Analog IP verification coverage is important metrics as it directly related to the guaranteed success. Manual verification often results in poor coverage or human intuition. The above methodology advocates an independent verification of analog macro. The test bench and test scripts developed using Ocean ensures all the verification accomplished as per the test plan. The designer must ensure that the design passes the test cases. Optimizer kind of tool does help in quick fixes.
Layout optimizer  is another add-on flow which is important for improving the productivity. Sometime without intervention of engineer, the layout can be optimized for new DRC or DFM rules. In addition to this the layout can be optimized to ensure the higher yield. In case of layout porting, the layout optimizer plays very important role.
The design methodology as per the Figure 2 ensures higher reusability of architecture, models, test bench, test scripts and design environment. The modular behavior of methodology helps the designer to handle the minor or major change in an efficient way. The robust verification flow does help to ensure the circuit performance as per the requirements.
SOC PLATFORM INTEGRATION
SOC platforms are proving a quicker way for SOC development. Once programmed, it enables hardware and software configuration and debugging at its operational speed. Often the platform consists of the models and synthesizable RTL code for digital components. The analog models are very basic verilog model which does not replicate the correct behavior of the block. It is important to have more accurate models in order to simulate in true mixed signal environment. A fast-spice simulation environment is recommended for verifying analog blocks in a true mixed signal environment.
CASE STUDY ON HIGH MULTIPLYING PLL
Phase Loop Lock systems are popular clocking system for many SOC needs. Many vendors spend huge capital to cater to the need of various flavors of PLL for their SOC customers. Also, PLL development goes in parallel to the digital process migration. Minimizing power, improving speed, reducing area, reducing jitter, process node changes etc are the common requirement changes those have been noticed in past. These changes become critical at ultra deep sub micron processes as higher substrate leakage, larger switching noise, etc impacts the PLL performance. It is also evident that the verification effort goes into verifying the PLL across the PVT corners are significantly high, due to the closed loop nature. The simulation time for PLL at worst case corners usually varies from couple of days to even a week time. Any iteration in design further causes huge schedule and effort variance. From Analog IP development perspective, it is important to address the above issues with optimum development cost and elapsed time.
The design methodology as per Figure 2, addresses few of the above stated issues. First and foremost, the requirement management of Analog IP plays important role in clear requirement elicitation. That helps to baseline the technical requirement and design goal clearly. An independent study on the uses of optimizer tool  has shown the benefit thru its feasibility analysis capability feature. This feature can be useful in decision making process during the Architecture Phase. Also, the tools can be helpful in optimizing the circuit at transistor level. The company claims that the tool can be useful in improving the yield too. We have observed that the use of accurate behavioral models for verifying the performance of PLL and lock conditions improves the overall productivity. During the development of behavioral models one need to include the simulation data of the sub circuits for all the process corners. For example, it is important to include the charge pump current value or VCO slope value for SS, TT, FF corners. Having accurate model helps to cut down the simulation time by 5x factor.
Figure 3: Comparison of VCO control voltage between SPICE and Verilog AMS model simulation
At TT corner, the simulation time taken by the model was 5x times less than a Fast Spice simulator. The model can be further used to validate the PLL performance to all the corners.
Often a large effort goes into development of Test bench and test scripts for the automation. The standardization of script development and test bench helps to cut down 5-10% of development effort. Proven test scripts also guarantee the simulation results.
The above design methodology also advocates the uses of porting tools for automatic migration of schematic and layout data base. A sanity check on signals and connections is highly recommended by experienced engineer to ensure flaw-less data. EDA company like In2Fab has been successfully demonstrated the layout porting exercise for various customers , . Inclusion of circuit optimizer, layout porting tools and uses of accurate models has been proved benefiting to many design teams. Statistical design techniques helps to improve overall yield and maximizing the investment goes into silicon process. At last we propose a detailed documentation which describes IP design, test plan, integration plan, modeling approach etc. A centralized knowledgebase may help IP vendor to stop re-inventing wheel every time. From customer perspective, robust IP reduces the SOC risk and hence increase the ROI.
The proposed design flow has a capability to handle many of the design challenges and to improve the overall productivity. It also offers higher reusability of design and robust test environment. As discussed in the PLL example, the agility of IP requirements can be addressed, if we divide the IP development activity in various phases and leverage the methodology to fulfill the requirements. We can cut down effort and schedule to even 50% by increasing reusability and automation in the development process. The proposed design methodology will act as an enabler for design & layout engineer and will help them to improve their efficiency. Simultaneously, this will help Analog IP vendors to keep their IP development plan as per the process trend.
1. TSMC 2011 second quarter investor conference (www.tsmc.com)
3. AnXplorer manual from AgO-inc