San Mateo, Calif. - I/O standards with transfer rates in the multiple-gigabit/second range are unquestionably a blessing to systems designers. Links such as Rapid I/O, HyperTransport or Rambus RaSer can reduce pin counts, permit levels of integration that would otherwise be impractical and enable new approaches to partitioning of high-performance systems.
Those advantages also add needed freedom for system-level designers, but there is a price to be paid. Integration of a mixed-signal block with sensitive inputs, frequencies in the gigahertz range and perhaps special electrical requirements may tax-or exceed-the capabilities of even the most experienced digital design teams. And in these lean times, very few system-on-chip teams have experienced high-frequency analog designers on call. Hence, the I/O interfaces that support these standards present a very interesting problem in intellectual-property (IP) integration.
Some IP vendors have a nearly turnkey approach: Here's the core for your process, and leave it alone. Others may take a hands-off attitude: Here's the core, call if you have questions. Naturally there's a wide spectrum of vendor relationships in between.
As a case study, the experience of Cadence Design Foundry (Livingston, Scotland) with a recently developed Rapid I/O interface module is instructive. Besides being a significant design effort in its own right, the module illustrates a number of important issues about IP integration and about relationships between design teams and design services vendors.
The core was developed in cooperation with Motorola Inc., which is pushing Rapid I/O as an interface for embedded-systems use. The design levers previous Cadence IP developed for the conceptually similar Xaui standard. It comprises three hardware layers: a physical-media-dependent attachment layer, a protocol-coding sublayer and a logic-and-transport layer. The latter two layers are implemented as digital designs, but the attachment layer includes some tricky analog content.
That part of the design includes a critical high-frequency serdes, a definitely nontrivial design, according to Gordon McKinnon, Cadence Design Foundry's business manager. Not only must the serdes be able to operate accurately at high frequencies, it also must be robust enough to be portable to a range of processes-usually without the benefit of specialized analog process modules-and must be nearly impervious to substrate noise coupling. To this end, Cadence has devised an architecture based not on the usual phase-locked loop approach, but on a phase interpolator for clock recovery. To its credit, the architecture has survived implementation in processes from 350 to 130 nanometers, McKinnon claimed.
Porting the core is straightforward, but not automatic, McKinnon said. The scope of the problem is simplified because most of the designs using the core have been targeted to Taiwan Semiconductor Man ufacturing Co., although at several process nodes. Generally, a couple of test chip iterations are required to get the serdes just right. The biggest problem Cadence has encountered in porting, McKinnon said, was brought about when TSMC, wrestling with voids in vias at 130 nm, changed its metal stack formula early this year.
"They changed the design rules and the impedance models," he said. "And when you change the interconnect resistance and capacitance in an analog circuit in the gigahertz range, that sends you back to change the circuit design."
Once Cadence has signed off on the serdes, the component is supplied to licensees as a hard macro, carefully isolated from the customer's digital design. That took some additional design work. Ordinarily the digital logic that implements the protocol-coding sublayer is intimately tied into the serdes. But in Cadence's approach, the serdes is a hard core using current-mode design, and the protocol-coding hardware is fully synthesizable. So the two h ad to be separated, and a very clear interface defined between them.
That interface also facilitated development of analog and digital simulation domains. The serdes exists as a Spice model that, in fact, extends into the surrounding digital circuitry, just to prevent surprises. It also exists as a behavioral Verilog model for use in digital verification. The serdes is wrapped in registers, so it behaves as a part of the synchronous digital design from the customer's point of view.
The interface also helps define the relationship between Cadence and its client. Cadence ensures that the physical-layer design functions to specifications and that the RTL for the other layers is correct. The customer is free to modify the RTL to differentiate its product. The wrapper around the serdes gives a clearly defined point of reference from which any problems can be examined. Digital designers can look back toward the interface to determine what is going on in the digital domain, and Cadence's analog team can work within the wrapper to ensure function and manufacturability of the analog circuits.