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IP / SOC Products Articles

• SuperSpeed USB 3.0: Ubiquitous Interconnect for Next Generation Consumer Applications (Jun. 22, 2009)
  To address the bandwidth limitations of the USB 2.0 interface, the USB Implementers Forum (USB-IF) released the SuperSpeed USB 3.0 specifications in November 2008. The USB 3.0 specification provides a maximum bandwidth of up to 5Gbps while limiting power consumption. In this white paper we present the features of the USB 3.0 protocol, discuss the new usage models it enables and compare it with some of the existing interface standards popular in the market today.
  
  
• Networks-on-Chip with Reprogrammable Interconnections (Jun. 11, 2009)
  One of ways for enlargement of ASIC based Systems-on-chip field of application is using of internal interconnection system based on reconfigurable Network-on-chip. In this article we suggest some variants of reconfigurable system-on-chip structure based on physical and virtual channels, evaluate their parameters. We suggest mathematical model for relative hardware cost of systems evaluation We compare hardware cost and throughput for these variants of systems.
  
  
• Tailored SoC Building Using Reconfigurable IP Blocks (Jun. 08, 2009)
  Increasing complexity, faster changing standards and shorter time to market ask for composing systems out of standard IP components. An example shows the construction of a System-on-Chip (SoC) based on standard IP components for a Digital Audio Broadcasting consumer application.
  
  
• Can MIPI and MDDI Co-Exist? (Jun. 08, 2009)
  Since MIPI and MDDI standards both target interfaces to cameras and displays on mobile devices, are two separate standards really needed?
  
  
• H.264/AVC HDTV Motion Compensation Soft IP (Jun. 04, 2009)
  This paper presents a motion compensation soft IP for H.264/AVC decoding based on the MoCHA architecture. The IP was designed in VHDL and validated by simulation and by prototyping on a Xilinx FPGA platform.
  
  
• H.264 High Profile: Codec for Broadcast & Professional Video Application (May. 28, 2009)
  High definition video content is becoming rampant as more and more countries are now transitioning into digital life. The ways to deliverHigh definition content in a bandwidth limited channel have become challenge in itself. To cater to such highly demanding broadcast & professional video markets, we require a compression / decompression standard that allows no compromise on the quality of the video that has to be broadcasted over a bandwidth constrained networks.
  
  
• Adopting An SOC-based Approach to Designing Handheld Medical Devices (May. 28, 2009)
  The rapid growth of the medical devices industry has seen a comparable increase in demand for handheld medical devices, from personal defibulators to continuous glucose monitors. Designing such devices can be a daunting task.
  
  
• A Re-Usable Level 2 Cache Architecture (May. 25, 2009)
  This paper presents the architecture of a high performance level 2 cache capable of use with a large class of embedded RISC cpu cores. The cache has a number of novel features including advanced support for data prefetch, coherency, and performance monitoring. Results are presented showing the performance improvement profile over a large class of applications.
  
  
• High Level Synthesis of JPEG Application Engine (May. 21, 2009)
  High Level Synthesis (HLS) technology and tools are used to transform high level behavioral model written in C, to synthesizable hardware in RTL . We have evaluated one such commercial HLS tool to create JPEG encoder RTL straight from C algorithm within a very short design time. This paper discusses the steps involved in automatic “Algorithm to RTL” transformation and compares the results with RTL developed using traditional method.
  
  
• A 0.79-mm2 29-mW Real-Time Face Detection IP Core (May. 21, 2009)
  A 0.79-mm2 29-mW real-time face detection IP core is fabricated in a 0.13-mm CMOS technology and its performance was evaluated. It consists of 75-kgate logic, 58-kbit SRAM, and an ARM AMBA bus interface.
  
  
• New Applications Areas Driving Higher Dynamic Range Converters (May. 18, 2009)
  With the advent of higher broadband speeds in the fixed line and wireless systems, the need for higher performing data converters has become apparent. In this article, we discuss the different standards that are pushing this trend and how single tone testing, in some cases, does not accurately determine the performance in communication systems.
  
  
• USB OTG: The only wired interface portable consumer products need? (Apr. 23, 2009)
  With so many portable product interfaces, UBS On-the-Go is perhaps the best choice in many situations
  
  
• Practical Design and Implementation of a Configurable DDR2 PHY (Apr. 20, 2009)
  To reduce the hassles presented to SoC designers by the DDR2 interface, many problems have been resolved by DDR2 PHY IP development. A DDR2 high speed PHY block is almost always developed as a full custom mixed signal design. There are many good reasons for implementing a full custom design, where every cell and every signal route is fully controlled. Such pre-defined, hard designs offer a way to deal with the tight timing budget of DDR2, which is in the range of a few tens of picoseconds. Another reason is the physical dimensions in which this block must fit. This paper presents through examples of the methods selected while performing physical implementation of the IP.
  
  
• Inside Ceva's high-performance XC core for 4G handsets, infrastructure (Apr. 16, 2009)
  In February CEVA announced a new family of high-performance licensable DSP cores, the CEVA-XC family, targeting 4G cellular applications, including LTE and WiMax -- for both handsets and infrastructure. BDTI went inside and took a look at the company's performance and features claims.
  
  
• Using an interface wrapper module to simplify implementing PCIe on FPGAs (Apr. 09, 2009)
  Stephane Hauradou compares various approaches to implementing PCI Express on FPGAs to the PLDA EZDMA module interface wrapper to provide a simple and robust user interface with PCI Express hard IP.
  
  
• Building advanced Cortex-M3 applications (Apr. 09, 2009)
  The ARM Cortex-M3 architecture provides many improvements compared with its predecessor, the popular ARM7/9, and is designed to be particularly suitable for cost-sensitive embedded applications that require deterministic system behavior. This article describes how developers can best utilize the advanced capabilities of the Cortex-M3 when designing embedded applications.
  
  
• SoC IP Interfaces and Infrastructure -- A Hybrid Approach (Apr. 06, 2009)
  This paper presents three generations of SoC designs beginning with a flat single AHB Bus based interconnect, followed by a multi-tier AHB/APB segmented communication infrastructure and finally our hybrid approach using both the AHB bus for control path operations and point to point BVCI connections through an internal crossbar for data flow. This architecture eliminates many of the dataflow bottlenecks common to SoCs and leaves the device constrained only by processing power and DRAM bandwidth. The power benefits of the architecture are also discussed throughout.
  
  
• Optimization of current-limiting solutions for USB 3.0 (Apr. 06, 2009)
  In addition to transfer speed enhancement in USB 3.0, the requirement for power supply is also increased to meet various peripheral demands. The article introduces the Polymeric Positive Temperature Coefficient (PPTC) device, which is an over-current protection device often used in the industry, and compares it with low-voltage solid-state switch for USB 3.0 applications.
  
  
• M-LVDS for true multipoint interfaces on busses--and more (Mar. 30, 2009)
  Multipoint, low-voltage differential signaling (M-LVDS) is an interface standard similar to LVDS. It provides the benefits of high-speed, low-power, and low-EMI transmission solutions to today's bus applications. M-LVDS is suitable for data, control, synchronization and clock signals.
  
  
• Integrated Power Management, Leakage Control and Process Compensation Technology for Advanced Processes (Mar. 16, 2009)
  This paper describes a unique suite of power management, leakage control and process compensation technology geared towards reducing power while optimizing performance. This integrated solution, including advanced algorithms, innovative circuits, unique devices and structures, software and manufacturing optimization methods, will be discussed. Silicon performance results will be reported.
  
  
• Pipeline vs. Sigma Delta ADC for Communications Applications (Mar. 16, 2009)
  The Analog-to-Digital Converter (ADC) is a key component in digital communications receive channels, and the correct choice of ADC is critical for optimizing system design. In this article, we discuss what design factors drive the selection of the ADC, how to specify the ADC and when to choose between a Pipeline ADC and a Sigma-Delta (Σ/Δ) ADC.
  
  
• Debug and testability features for multi-protocol 10G Serdes (Mar. 09, 2009)
  The paper describes the design-for-test (DFT) features of a 10.3125Gb/s Serdes and other such high datarate IP as XAUI, PCIe, and others. It is shown that extensive testability can be implemented in a high data-rate Serdes. The paper describes the bench-test and characterization features, as well as wafer and production test considerations.
  
  
• The VP8 video codec: High compression + low complexity (Mar. 02, 2009)
  On2 VP8 achieves high compression with a bitstream that is less compute intensive to decode than either its predecessor (VP7) or competing technologies like H.264. Here's how it works.
  
  
• PCI Express Gen 3 Simplified (Feb. 27, 2009)
  In early 2008, the PCI-SIG announced the establishment of a workgroup chartered with the development of the next generation of PCIe " the PCI Express Base Specification 3.0, or PCIe Gen 3. The Gen 3 specification is yet another step forward in enhancing the usefulness of the PCIe protocol by doubling the effective bandwidth and adding protocol enhancements to increase end-system performance.
  
  
• Analysis: BDTI benchmarks the CEVA-TeakLite-III (Feb. 26, 2009)
  BDTI has released BDTI DSP Kernel Benchmarks results for the CEVA-TeakLite-III core from CEVA. The CEVA-TeakLite-III competes with a range of general-purpose DSP and CPU cores from vendors such as VeriSilicon, ARM, and MIPS, and also with application-specific audio solutions, such as Tensilica's 330HiFi audio core and ARC's Sound Subsystems cores.
  
  
• How to pick a RapidIO switch (Feb. 23, 2009)
  Designers have many different options for implementing a RapidIO interconnect. This article outlines the decision factors that designers should consider, organized by project development phases: system design, implementation, system verification, and system evolution. A last section discusses support services, which impact all stages of project development.
  
  
• DDR SDRAM Controller IP Designed for Reuse (Feb. 19, 2009)
  This paper deals with reusability issues in the development of a double data rate (DDR) SDRAM controller module for FPGA-based systems. With our approach, it is possible to generate a highly reconfigurable DDR controller that minimizes the recoding effort for hardware development.
  
  
• Dynamic instruction set load-in method for Java SoC (Feb. 12, 2009)
  There are varieties of embedded systems in the world, it’s a big challenge to optimized the instruction sets of SoCs according to different systems’ working environments. The idea of dynamic instruction set is a good method to achieve the embedded system’s re-configurability. This paper presents a convenient method for a Java processor to work with dynamic instruction set in the form of FPGA or ASIC.
  
  
• Migrating from SPI 4.2 to SPI 5 IP Core - Architectural Changes and Re-usability (Feb. 09, 2009)
  This article discusses the architectural changes and IP re-usability scope for modifying an existing SPI 4.2 Transmitter and Receiver IP Core. SPI 4.2 and SPI 5 have a great deal of functional similarity which makes this IP migration smoother. The paper considers an existing SPI 4.2 IP core and examines the architectural changes and re-usability of the sub-modules. The addition of a few modules, which are a part of SPI 5 protocol, is also highlighted.
  
  
• A Platform for Performance Validation of Memory Controllers (Feb. 02, 2009)
  With growing gap between processor and memory speeds, the memory bandwidth has become performance bottleneck for media applications. The memory controller designs are getting optimized to reduce the latencies added by them. It is necessary to prove the performance of memory controller on prototypes. It has been observed that the performance calculated in simulations is very difficult to achieve on prototype board. This is mainly because of subsystem limitations.