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Verification IP Articles

• Architecting the OCP uVC verification component (Jan. 13, 2009)
  Architecting effective verification components for something as flexible as the Open Core Protocol requires a detailed understanding not only of the corresponding specification, but also the environments and methodology in which the verification component will be used. This article demonstrates how two key aspects of OCP - profiles and transactions - were adopted as fundamental building blocks for the architecture of a verification component targeted at constrained-random validation of OCP components and systems.
  
  
• Performance Verification Methods Developed for an HDTV SoC Integrating a Mixed Circuit-Switched / NoC Interconnect (STBus/VSTNoC) (Sep. 15, 2008)
  This paper presents the performance verification methods that were set up and used for a SoC recently developed at STM. The SoC is a one-chip satellite HDTV set-top-box decoder IC. It integrates many memory-bandwidth demanding IPs sharing one or two DDR2 memories.
  
  
• Learning not to fear PCI Express compliance (Aug. 12, 2008)
  
  
  
• Achieve PCIe compliance and interoperability in your IP core-based design (Jul. 14, 2008)
  The quick adoption of PCIe technology has resulted in a market flooded with many different implementations of the PCIe specification. While, theoretically, each of these implementations should be compliant with the specification and interoperate with all other implementations, the reality is that non-compliant and non-interoperable devices do make their way to the marketplace.
  
  
• Mixed-Signal Verification for USB 2.0 Physical Layer IP (Jun. 09, 2008)
  A well planned verification flow for a mixed-signal IP is required to achieve the highest quality of the IP performance with the expected design specifications. The aim of this paper is to present a mixed-signal verification flow for the Universal Serial Bus physical layer IP.
  
  
• Verification of IP Core Based SoC's (Apr. 14, 2008)
  In an IP-Core based SoC design. A streamlined verification and analysis flow can contribute significantly to the success of a product. A strategy is devised for a more streamlined approach in IP-core based SoC verification which helps in smooth transition from design to chip tape-out stage.
  
  
• Verification IP Reuse For Complex Networking Asics (Apr. 02, 2008)
  Maximizing verification IP reuse improves verification productivity. The International Technology Roadmap for Semiconductors (ITRS) projects that 75 percent of design/verification productivity improvement will come from IP reuse and 25 percent from improved EDA tools, flow, or methodologies.
  
  
• To develop or buy a Verification IP (Jan. 17, 2008)
  The most important benefit of buying the VIP rather than making it is that a commercial VIP provides a totally independent, clear and unambiguous interpretation of the specifications of a protocol for which it is designed. Until the time when the specifications themselves are written such that they have no ambiguity, this independent interpretation is invaluable.
  
  
• OCP VIP: A cost effective and robust qualification process for multimedia and telecom SoC designs (Jan. 09, 2008)
  Open Core Protocol (OCP) flexibility, configurability and scalability are the key elements making OCP massively used and successful into major electronics markets. Upon these characteristics any IP can adopt the best interface for the connection to the OCP backbone with immediate benefit for bandwidth capability. This has made OCP broadly used in many applications like multimedia, telecom and gaming.
  
  
• Development of Verification Environment for Layered Protocol using SystemVerilog (Jul. 02, 2007)
  This paper explains how individual layered specific verification components such as, Transactor, Checker, Monitor which can be developed using SystemVerilog can be reused when you have all the layers connected at the sub-system and system level, and hence maximizes the verification productivity gains.
  
  
• e Verification Environment for FlexRay Advanced Automotive Networks (May. 14, 2007)
  FlexRay is the vehicle networking standard being backed by all major automotive manufacturers because it is fast and flexible while being reliable and deterministic. NXP (formerly Philips) Semiconductor is a founding member of the FlexRay Consortium and has invested heavily in a comprehensive e verification environment for FlexRay, which IPextreme is taking to market.
  
  
• Verifying Configurable Verification Interfaces Using OCP (May. 10, 2007)
  This article presents a basic overview of OCP covering both the basic operation and configuration files. It then introduces a configurable OCP formal verification IP generator that automatically creates appropriate OCP properties for a specific to design implementation of the protocol. These concepts are used to demonstrate a silicon-tested method of developing a verification plan for OCP designs.
  
  
• A Platform-Based Technology for Fault-Robust SoC Design (Mar. 12, 2007)
  In this paper it is proposed a systematic platform-based technology, in which a library of reusable IPs (HW and SW) is used together with a set of tools and methodologies to find the optimum solution in this design space, following the IEC61508 guidelines.
  
  
• Complex SoC Verification using ARM Processor (Mar. 01, 2007)
  A verification environment with a mix of C tests for debugging (for embedded processor) and verilog test bench for monitors and automated checkers is used for successfully verification of an ARM based SoC design. This paper provides more detailed illustration that combines C (embedded test cases) and Verilog test bench for system level verification and also introduces verification techniques that helps in reducing verification time of SoC's .
  
  
• Achieving completeness in IP functional verification (Feb. 12, 2007)
  This article formalizes the concept of best possible verification quality -- completeness -- and describes a methodology, field-proven on many complex module and intellectual property (IP) designs, that tells you when verification is complete. To demonstrate the results, it summarizes the verification of a protocol processor IP from Infineon.
  
  
• USB 2.0 PHY Verification (Jan. 15, 2007)
  In this paper we present a Vera-based reusable environment to verify a USB 2.0 PHY that addresses some of the problems of a typical PHY Verification. Thus, we present the developed VIPs such as monitors, response checkers and functional coverage object needed to be re-used for multiple PHY implementations, as well as potentially in an integrated Controller/PHY testbench.
  
  
• Verification IP takes a broader role (Aug. 07, 2006)
  
  
  
• Transaction-based Debug of PCI Express Embedded SoC Platforms (Mar. 09, 2006)
  
  
  
• A Unified DFT Verification Methodology (Feb. 20, 2006)
  
  
  
• Advanced Techniques for Building Robust Testbenches with DesignWare Verification IP and Reference Verification Methodology (RVM) (Feb. 06, 2006)
  
  
  
• Unique Approach to Verification of Complex SoC Designs (Feb. 06, 2006)
  
  
  
• Designing a CE-ATA Verification Environment for SoC Applications (Jan. 12, 2006)
  
  
  
• Large Memory Modeling (Dec. 12, 2005)
  
  
  
• PCI Express verification underscores need to plan (Nov. 07, 2005)
  
  
  
• Verification moves to a higher level (Oct. 03, 2005)
  
  
  
• Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Reference Verification Methodology (RVM) (Aug. 08, 2005)
  
  
  
• Efficient Verification of CAN based System (Jul. 07, 2005)
  
  
  
• A comprehensive approach for verification of OCP-based SoCs (May. 05, 2005)
  
  
  
• Designing Using the AMBA (TM) 3 AXI (TM) Protocol -- Easing the Design Challenges and Putting the Verification Task on a Fast Track to Success (May. 05, 2005)
  
  
  
• Using Vera and Constrained-Random Verification to Improve DesignWare Core Quality (Mar. 04, 2005)