Compact clock-generation PLL with 1.0GHz VCO for system and interface clocking applications.

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Design impact of 450mm transitionCollaborative Advantage - Steve SchulzDec. 05, 2012 |
There’s been lots of news lately on the industry transition to 450mm wafers. Recent headlines include coverage on the G450C’s 2015-16 target 10nm pilot line, TSMC’s $10B investment in 450nm, TSMC’s rollout delay from 2015 to 2018, and lithography being the big schedule bottleneck (yet again). The media have covered expectations of 400% higher starting wafer costs, a 20-50% increase in equipment costs, and fallout on the very health of the semiconductor equipment industry. There has also been some positive press too, including potential benefits at advanced nodes, such as 2.5x the number of die/wafer, and 20-25% less cost per die at 22nm and below.
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