If you're working on the design of mobile devices, the emerging PCIe over M-PHY (M-PCIe) standard could become very important to you. And if you'd like to learn more about it, a recently archived Cadence webinar explains what M-PCIe is, what applications will use it, how it differs from PCI Express (PCIe), and what Cadence offers in support of system-on-chip (SoC) design with M-PCIe.
The webinar was presented June 28, 2013 by Arif Khan (right), product marketing director for the SoC Realization Group at Cadence. (Khan is also a Cadence blogger, and he recently wrote about how Cadence was the first company to demo a complete M-PCIe PHY and controller solution at the recent MIPI and PCI-SIG conferences).
Khan began the webinar with a look at the evolution of PCIe. This protocol, he noted, provides a scalable, high-performance I/O interconnect for computing and communications applications. It started in 2002 with PCIe Gen1, which provides up to 2.5 GT/s. In 2006, Gen2 raised this performance to 5 GT/s, and in 2010 Gen3 claimed 8 GT/s. In 2011 PCIe Gen4 was announced (16 GT/s), but the spec is not yet complete.
PCIe is widely used in applications such as storage, networking, supercomputing, test equipment, and FPGA-based systems. But it is typically not used for mobile applications because of its power consumption. That's where M-PCIe, introduced in September 2012 by the PCI Special Interest Group (SIG) in cooperation with the MIPI Alliance, comes in.
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