Cadence this week (May 19, 2014) is announcing the first DDR4 PHY IP built on TSMC's 16nm FinFET process. The 3200Mbps DRAMs that can take best advantage of this capability aren't shipping in volume yet - but you can "future-proof" your 16nm SoC design by using a DDR4 controller and PHY that can scale up to 3200Mbps as the parts become available. Further, the availability of 16nm FinFET support for very high-speed memory might provide yet another incentive for considering that process node.
DRAMs today are available at 2133Mbps, a speed supported by both the DDR3 and DDR4 standards. You can easily get this performance in a 28nm process. (Cadence, in fact, announced in January that its DDR4 PHY IP achieves 2667Mbps in 28nm). But according to Kishore Kasamsetty, product marketing director at Cadence, you really need to go to a FinFET process to get 3200Mbps performance.
And who needs that performance? The first adopters will probably be enterprise applications such as servers, network switching, and storage fabrics. These applications can also take advantage of the overall power, performance, and area advantages of a sub-20nm process.
"We don't know exactly when DRAMs rated higher than 2400Mbps will go into high volume, but if you're designing today on an advanced process using IP optimized to take advantage of the higher performance offered by the FinFET process, you are set for the future" with the Cadence DDR4 PHY, Kasamsetty said.
As he pointed out, you don't want to have to redesign your DDR4 PHY interface when the new parts come out. Even if your application needs only a maximum of 2400Mbps performance today, the Cadence PHY IP that's capable of 3200Mbps operation will provide additional robustness and improved system margins. As the application needs increase, and higher speed DRAMs are available, designers can reuse the same DDR PHY IP without having to do a costly redesign or procure new IP.
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