Silicon-Sharing Fits 200K Gate Design into 40K Gate FPSLIC II's, Cuts Power Drain by 97%
San Jose, California, May 2, 2005 Atmel Corporation (NASDAQ: ATML), a global leader in the development and fabrication of advanced semiconductor solutions, announced today the introduction of its AVR-based FPSLIC® II, the industry's first family of dynamically reconfigurable systems-on-chips (SoCs) allowing multiple interfaces, peripherals and/or operators to share the same silicon at different times.
"Silicon sharing" is extremely important in power-and space-constrained systems, such as new generation mobile phones, PDAs, notebook computers, and printer/fax machines. Increasingly these devices must perform multiple functions (e.g. camera, MP3 player, phone) without sacrificing battery life, product size or product cost.
FPSLIC II's silicon-sharing capability is enhanced by Atmel's back-end, reconfiguration EDA tools. The tools are the first to automate the implementation, timing, and control of the silicon-sharing process. Previously, the design of silicon-sharing systems was essentially impossible because, even though some FPGAs can be reconfigured during operation, until now, there have been no tools to automate reconfiguration control and timing. Atmel is the first programmable SoC vendor to provide such EDA support.
The FPSLIC II dynamically reconfigurable programmable SoC integrates a 25 MIPS, 8-bit AVR processor, with 36 KB program/data SRAM, a hardware multiplier, peripherals and a dynamically reconfigurable FPGA, with 256 to 2300 core cells. A single piece of silicon can implement multiple, interchangeable peripherals, computational operators, and bus interfaces, including UART, SDIO, PCI, PCMCIA, HDLC, and Ethernet.
The main obstacles to silicon-sharing has always been ensuring that the correct functionality is loaded into the FPGA at the correct time and that functions are not loaded on top of each other. Since either of these can cause catastrophic system failure, adding new features has typically required the addition of dedicated silicon (i.e. a larger FPGA), increasing both power consumption and system cost. Atmel has solved this problem by placing a configuration controller, two DMA controllers, a dedicated FPGA-to-AVR interface and a "virtual socket" in the FPGA portion of the programmable SoC. The "virtual socket" is populated from a library of previously designed peripherals, interfaces or operators that share the same silicon.
Atmel provides a library of reference designs for interfaces, peripherals and hardware accelerators that includes Ethernet, memory, SPI, SDIO, multimedia card, DMA, speech synthesis, ADPCM, audio codec interfaces, and DES/triple DES encryption algorithms. The company will introduce a library of pre-routed "drag-and-drop" co-processors and interfaces later this year. Designers may also use Atmel's System Designer EDA tool to develop custom IP for silicon sharing.
Reconfiguration Process - The on-chip AVR and reconfiguration controller manage the reconfiguration process. Based on inputs to the Reconfiguration Designer tool, the configuration controller signals the AVR when it is time to reconfigure the virtual socket, which IP block to load, the number of cycles required for execution and other constraints. At the time the design is done, System Designer checks that all the required library elements exist, places and routes the design, and generates appropriate bitstreams for the entire hardware design, including the virtual socket for the reconfigurable elements. The reconfigurable elements (peripherals, interfaces, etc.) are individually placed and routed to fit the virtual socket. System Designer then assembles all bitstreams into a "master" bitstream, with memory pointers, that is stored in external memory.
FPSLIC II's virtual socket can be reconfigured at any time during system operation from a library of pre-compiled IP cores stored in external flash memory. At 25 MHz, reconfiguration takes less than 9 ms.
Design Flow The IP libraries for reconfigurable designs are done in the same way as ordinary FPGA designs. Existing VHDL or Verilog designs can be used as library elements or designers can use Atmel's System Designer FPGA design tool suite to implement custom peripherals, arithmetic operators, interfaces or control logic. Designs can also be developed in C-based Electronic System level and synthesized into an HDL tool using the Celoxica® tool suite. There is no silicon penalty for using Celoxica for computational functions and about a 10% penalty for using it to design interface or control logic.
Higher Throughput for Lower Power, Less Cost - FPSLIC II power consumption is s 50 uA in standby and 2-3mA/MHz during operation. With a 4 MHz clock, the 8-bit, hardware-accelerated FPSLIC II and external memory consume 9.2 mA and can execute the same functions as, a 200 MHz 32-bit RISC processor with four times the power drain. Using an FPGA without silicon-sharing would require a 200,000 gate device with power drain of 300 mA 32 times the power consumption of FPSLIC II.
Pricing and Availability - FPSLIC II family devices are available now, with FPGA densities, from 256 to 2300 core cells. in Green lead-free 144-pin TQFP and 208PQFP packages, in industrial temp 40 degrees C + 85 degrees C. Prices are as follows in quantities of 100,000 units:
- AT94K05AL-25BQU 256 core cells $4.50
- AT94K10AL-25BQU 512 core cells $6.90
- AT94K40AL-25DQU 2300 core cells $12.90
1: These tools were jointly developed by Atmel and the ReCONF2 (EU-IST-2001-34016) project with the cooperation of the Czech Academy of Sciences' Institute for Information Theory and Automation (UTIA).
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