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Arteris Announces STMicroelectronics Use of NoC for Next Generation Wireless Infrastructure Platform; Pioneering Network on Chip Technology Delivers Higher SoC Performance While Reducing Design CyclePARIS--March 15, 2006--Arteris SA, a leading provider of Network on Chip (NoC) solutions today announced that STMicroelectronics has selected Arteris for advanced on-chip communication in its Wireless Infrastructure SoC Design. Arteris NoC delivers twice the performance of other interconnect solutions while operating with existing on-chip IP standards. "Today, although ST recently disclosed an exciting research breakthrough in Network-on-Chip architectures, Arteris has the most industrialized on-chip interconnect, which delivers significant value by helping us achieve new classes of performance while reducing our design cycle," said Daniel Abecassis, General Manager of ST Wireless Infrastructure Division. "The Arteris NoC technology natively enables us to reuse all of our SoC IP and the architecture exploration methodology of Arteris matches our Wireless Infrastructure Design environment." "In highly competitive markets our customers are facing increasing demand to produce the highest performance products within the shortest amount of time," said Alain Fanet, Chief Technology Officer of Arteris. "Our expertise in on-chip interconnect technology enables ST to design complex wireless communications devices. Our NoC technology achieves higher communication throughput, twice as fast as existing interconnect architectures." Arteris' NoC Solution will constitute the on-chip communication in the new generation of Wireless Infrastructure devices, handling high bandwidth traffic between multiple processors, DSP engines, and high-speed memories. The Arteris solution fits within standard high-level EDA tools flows, and has proven to provide significant performance and IP integration improvements while, in many cases, using fewer gates than traditional bus-based approaches. About Arteris Arteris, SA, provides Network on Chip solutions to transport and manage the on-chip communications within complex System-on-Chip (SoC) integrated circuits, increasing performance, reducing number of global wires, with lower power utilization while enabling the most complex, IP-laden designs. It allows chip developers to implement efficient and high-performance Network-on-Chip (NoC) designs, overcoming limitations of traditional layered or pipelined bus-based architectures. Arteris' technology is scaleable in terms of the number of IP blocks designers can network, as well as with deep submicron silicon manufacturing processes. The NoC solutions are compatible with existing design flows and with IP interface standards. The Paris-based company operates globally with offices in Boston and San Jose, California. Arteris has raised more than $12 million in equity investment from an international set of venture capitalists, including Crescendo Ventures, Techno Venture Management and Ventech. More information can be found at http://www.arteris.com.
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