Digital Blocks Announces its ''Try Before You Buy'' IP Core Evaluation Program
Prospective customers can evaluate Digital Blocks VHDL / Verilog IP cores prior to licensing, in a variety of formats.
GLEN ROCK, New Jersey, April 24, 2006 – Digital Blocks, a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for embedded processor system designers, today announces the “Try Before You Buy” IP Core Evaluation Program for all product offerings. Prospective customers have one-of-three options to evaluate a Digital Blocks IP Core: (1) Modelsim compiled simulation-only model with testbench; (2) Time-limited hardware model programmed into an FPGA; and (3) Altera OpenCore Model for evaluation within Quartus II or Altera FPGAs.
Currently, prospective customers can evaluate Digital Blocks’ DB8259A Programmable Interrupt Controller, which maintains the original static design of the Intel 8259A and Harris / Intersil 82C59A devices, the DB8259S Programmable Interrupt Controller, which adds a clock for an all synchronous design, and the DB6845 CRT Controller.
For time-limited hardware model evaluation, Digital Blocks supports Actel, Altera, Lattice, Quicklogic, and Xilinx, FPGAs.
Customers interested in evaluating Digital Blocks’ IP should fill out the IP Core Evaluation Request form at Digital Blocks’ web site, www.digitalblocks.com.
About Digital Blocks
Digital Blocks designs silicon-proven IP cores for technology systems companies, reducing customer’s development costs and significantly improving their time-to-volume goals. Digital Blocks is located at 587 Rock Rd, Glen Rock, NJ 07452 (USA). Phone: 1-201-251-1281; Fax: 1-208-379-1012; On the Web at www.digitalblocks.com
|
Digital Blocks Hot IP
Related News
- Actel Lets Customers "Try Before They Buy" with New Web-Based IP Core Evaluation Program
- Scottish initiative adds online 'try-before-buy' cores for IC designs
- Siemens joins Intel Foundry Services' EDA Alliance program
- Digital Blocks Celebrates 14 Years of Offering 82xx Peripheral Replacements
- Actel's CorefIR v4.0 Delivers Configurable Digital Filter Generation for Rtax-DSP with On-Chip Math Blocks
Breaking News
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
- TSMC Reports First Quarter EPS of NT$8.70
- Brisbane Silicon publishes DPTx 1.4 IP Core
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
Most Popular
- U.S. Subsidy for TSMC Has AI Chips, Tech Leadership in Sight
- Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
- Zhuhai Chuangfeixin: OTP IP Based on 90nm CMOS Image Sensor Process Technology Successfully Mass Production
- Silvaco Announces Expanded Partnership with Micron Technology
- OPENEDGES Unveils ENLIGHT Pro: A High-Performance NPU IP Quadrupling its Previous Generation's Performance
E-mail This Article | Printer-Friendly Page |