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Microtronix Launches High Performance Multi-port SDRAM Memory Controller IP Core

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Boosts memory performance by more than 6 times over other standard memory controller IP Cores.

LONDON, Ontario -- August 30, 2006 Microtronix today launched a High Performance Multi-port SDRAM Memory Controller IP Core which boosts memory performance by more than 6 times over other standard memory controller IP Cores.The core is ideal for streaming video applications and supports up to 1024 x 768 (true colour) 32-bit display resolution. said Philippe Morin, VP Sales & Marketing. The core provides a complete, easy-to-use solution to interface with a wide variety of SDR and DDR SDRAM memory devices.The memory controller is optimized for the Altera Stratix and Cyclone family of programmable logic devices. The IP Core is Altera SOPC Builder Ready and integrates easily into any SOPC Builder generated system.

The Microtronix High Performance Multi-port SDRAM Memory Controller IP Core is years ahead of currently available standard SDRAM Memory IP Cores. There has never been a better time to switch to Microtronix, said Norman McCall, Microtronix President.The IP Core operates independent of the system clock enabling the memory to be clocked at its maximum frequency.The DDR Memory Controller IP uses a proprietary technology which simplifies memory interface design by removing the need for extra resynchronization clocks and maximizes the performance of the memory system.

Performance features:

• Multi-port system bus interfaces
• Optimized for streaming data applications
• Configurable cache size
• Avalon random and streaming bus support
• Unique independent DDR Round-Trip capture scheme
• Memory clock independent of system clock speed
• Optimized cache minimizes memory wait-states

• Supports SDR & DDR memory devices
• Configurable data width (1 - 32-bits)
• Memory clock independent of system clock
• Two local configurable system ports
• Altera SOPC Builder Ready
• IP functional simulations models (VHDL & Verilog)
• Support for OpenCore Plus evaluation

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