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SLE, a Tundra Division, Offers High-Speed Interlaken Interconnect Protocol IP CoreSilicon Logic Engineering Develops Scalable IP Core for Next Generation Communications Equipment EAU CLAIRE, WI - January 23, 2007 - Silicon Logic Engineering Inc. (SLE), a high-end semiconductor design services division of Tundra Semiconductor Corporation today announced the development of a licensable Interlaken protocol IP core for use in ASIC or FPGA designs. SLE's Interlaken IP Core is scalable, with early versions providing from 10Gbps to 60+Gbps bandwidth across the interface. Future versions will provide over 120Gbps of bandwidth. This scalability ideally suits Interlaken for multiple generations of future network switches, routers and storage equipment. The scalability is achieved through the combination of the SERDES speed (3.125Gbps to 6.375Gbps) and a variable number of SERDES lanes (1 to 24). Designed and tested to be easily synthesizable into many ASIC and FPGA technologies, SLE's Interlaken IP Core was uniquely built to work with off-the-shelf SERDES from most leading technology vendors. Using the vendor specific proven SERDES allows SLE customers to quickly integrate the Interlaken IP Core into the customer's technology of choice. The open Interlaken specification was co-written by Cortina Systems and Cisco Systems to provide a far more scalable chip-to-chip interface protocol than previous protocols. Interlaken combines the advantages of the popular SPI4.2 and XAUI interfaces by building on the channelization and per channel flow control features of SPI4.2, and reducing the number of chip I/O pins by using high speed SERDES technology, similar to XAUI. Tundra's Vice President of Design Services, Jeff West, said today "Tundra has again demonstrated leadership on interconnect technologies by adding Interlaken to its portfolio of IP and services and by working with our partners to provide our customers with innovative solutions". "By working with SLE, customers can take advantage of Interlaken, an open standards high performance system interface for communication equipment," said Zino Chair, Vice President of Marketing, Cortina Systems. "Interlaken enables silicon suppliers to scale their components to 40Gbps and beyond, simplify designs and reduce development cost.""Users of SLE's Interlaken IP will find that it is easier to evaluate, integrate, and prototype than previous interconnect IP," said Matt Weber, Senior Hardware Engineer and Lead Designer, SLE. "SLE development is well underway and we are currently working with early customers and major ASIC and FPGA vendors to provide Interlaken in multiple technologies, just as we did with our SPI4.2 IP." Product Availability About Tundra About Silicon Logic Engineering, Inc. About Cortina Systems
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