Tensilica's New Energy Estimator Tool Guides Designers to Energy-Efficient SOC Architectures

Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)

Xenergy Provides Immediate Power and Energy Estimates so Intelligent Trade-offs Can Be Made Early in Design Cycle

SANTA CLARA, Calif. – February 26, 2007 – To address the growing need to pro-actively reduce power consumption in embedded systems, Tensilica, Inc. today announced the Xenergy estimator, a unique energy estimator for both Xtensa configurable processors and Diamond Standard processors. By using the Xenergy tool to optimize for energy early in the SOC (System On Chip) design cycle, designers can cut processor and local memory energy requirements by up to half by making intelligent design trade-offs.

“Xenergy will naturally appeal to designers of portable, battery-driven devices such as cellular phones and personal media players, but also to designers of complex SOCs in home entertainment and networking devices where heat is becoming a huge issue,” stated Chris Rowen, Tensilica’s president and CEO. “Tensilica is the first company to provide a realistic way to easily estimate the overall energy impact of different processor configurations and extensions together with application code tuning on each processor with its memory subsystem. The improvement in power at the architectural level is quite dramatic and productive, often dwarfing the power savings painfully achieved at the RTL and physical design levels.”

Impact on Processor Design

Total energy to complete a task (power dissipated over time taken for the task to complete) can be dramatically reduced by customizing a Tensilica Xtensa processor. Sample results (table) show that with identical process technology, the energy improvement from processor customization can range from 2x to 83x.

Configuration		Dot Product	AES	Viterbi	FFT
Baseline Xtensa Processor	K Cycles	12	283	280	326
	Energy (µJ)	3.3	61.1	65.7	56.6
Optimized Xtensa Processor	K Cycles	5.9	2.8	7.6	13.8
	Energy (µJ)	1.6	0.7	2.0	2.5
Energy Improvement		2X	82X	33X	22X

The chart above shows the impact of extending the processor and tuning the C code, but does not assume changes in basic software algorithm, changes in memory sizes or use of assembly code.

Cycle by Cycle Energy Consumption Estimation

The new Xenergy energy estimator works by computing a power-consumption estimation per-cycle for each different instruction of an Xtensa configurable processor or Diamond Standard processor. For each user-defined instruction extension in an Xtensa processor, created using Tensilica’s powerful TIE (Tensilica Instruction Extension) language, Xenergy creates an energy estimate for the newly created instruction, including modeling the energy consumed by all locally attached memories that are active for a given instruction. Then, using the instruction profile created by Tensilica’s pipeline accurate instruction set simulator, a detailed energy consumption profile is created for the user’s specific application code.

The Xenergy tool is used during the process of configuring an Xtensa processor. Designers can immediately see the effect on total energy consumption when they add configuration options (multipliers, DSP engines, a floating point unit, and many additional configuration choices) and designer-defined instructions. They can see the effect of different interface options as well as memory subsystem options.

A Focus on Total Energy Consumption

A focus on total energy consumption is key. Too often, designers will focus on a static milliwatts per megahertz (mw/MHz) power figure, but ignore the total energy consumption of the workload. For example, a designer may add a set of custom instructions to a processor that increase the total size of a processor core, which increases the average power per clock cycle (increasing the mW/MHz). But if that custom instruction set addition dramatically lowers the total clock cycles required to perform a given functional workload (a target C code application) then the total energy consumed (power-per-cycle multiplied by total cycle time) can be reduced. Example: an increase in power per clock of 20% is offset by a 3x speed up in instruction execution. The mW/Mhz power consumption increases 20%, but total energy consumption is actually reduced by 60%. The reduction in required execution cycles allows the system either to spend much more time in a low-power sleep state, or to reduce frequency and voltage, leading to a sharp reduction in both dynamic and leakage power.

The inclusion of memory power consumption is another key aspect to the new Xenergy tool. Imagine a scenario where designer-defined processor extensions are used to create custom state registers and register files within an Xtensa processor core, not to appreciably improve execution performance, but instead aim at significantly decreasing accesses to local memory, thus decreasing overall energy. The Xenergy program points out this energy decrease, making it easy for the designer to weigh area, performance and power trade-offs early in the processor configuration process.

Impact on Software Design

The Xenergy energy estimator is also useful for optimizing software, even on completed chips where the processor – whether it is an Xtensa configurable processor or a Diamond Standard core – cannot be changed. Traditionally, software developers tune their code for performance or code size using Tensilica’s standard profiling tools. Now they can use the Xenergy tool to fine tune their C code to reduce energy dissipation by the processor and its memories. For example, a developer might use the feedback provided by the Xenergy tool to decide to restructure the allocation of data structures in local and main memories to reduce memory and bus accesses, which will lower overall energy expenditures.

Pricing and Availability

Tensilica’s Xenergy tool is available now as part of a Tensilica Software Development Kit license, which includes all software development tools, the instruction set simulator, and the Xtensa Xplorer™ design environment. For users of the Diamond Standard series of processors, pricing for the Software Development Kit starts at $1000 per seat per year for a node locked license. For Xtensa processor users, pricing for a Software Development Kit starts at $2000 per seat per year for a floating node tool seat.

About Tensilica

Tensilica offers the broadest line of controller, CPU and specialty DSP processors on the market today, in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. Tensilica’s low-power, benchmark proven processors have been designed into high-volume products at industry leaders in the digital consumer, networking and telecommunications markets. All Tensilica processor cores are complete with a matching software development tool environment, portfolio of system simulation models, and hardware implementation tool support. For more information on Tensilica's patented approach to the creation of application-specific building blocks for SOC design, visit www.tensilica.com.