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MOSAID Delivers Silicon-Proven PLLs at 65 Nanometers
OTTAWA, Ontario – April 10, 2007 - MOSAID Technologies Incorporated (TSX: MSD), a leading provider of high-performance, flexible semiconductor intellectual property (IP), today announced working silicon for its PLLs at the 65nm CMOS process node. MOSAID's PLLs were fabricated in both standard logic and low-power 65nm process nodes at a leading foundry. SoCs at 65nm include many IP cores which often have different frequency requirements. Implementations are simplified using one or more of MOSAID's configurable, high-performance PLLs. With PLL IP that is already proven at 65nm, designers reduce the risk and development cost for chips that use this IP and the end products in which they are embedded. "Many SoC designs, including consumer product SoCs, are quickly moving to the 65nm process node to reduce cost and increase functionality," said Michael Kaskowitz, Senior Vice President, Semiconductor IP, MOSAID. "Our 65nm silicon-proven PLL IP gives our customers time-to-market and flexibility advantages over the competition." MOSAID's fractional-N PLL is a fully integrated, programmable, low-power, high-performance Delta-Sigma, Fractional-N product. It is optimized for line-operated and battery powered applications at system clock rates as high as 3.2GHz. The large fractional multiplication range of MOSAID's PLL enables it to address many markets and applications with a single, low-cost crystal frequency, thus reducing inventory, delivery time and bill of materials (BOM) cost. Applications for these PLLs include frequency generation for audio and video decode/encode, interface standards, graphics processing, and network communications. Datasheets for 65nm MOSAID PLLs are available from the MOSAID Customer Center at www.mosaid.com. MOSAID's Fractional-N PLL is also available in 80nm, 90nm and 130nm process geometries. About MOSAID
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