Dolphin Integration announces its ultra low power, low leakage and High density 65 nm ROMs and RAMs
France, October 11, 2007 -- DOLPHIN Integration marks their presence at 65 nm, with the patented tROMet Phoenix, optimized for ultra high density and very low leakage, as well as the spRAM Uranus optimized for Low power and Low leakage.
Typically, the silicon area of a 6-Mbit instance ROM in 65 nm will decrease as far as 0.63 mm2 with only 1.2 uA leakage current, thanks to the key “two-in-one” patent.
For a RAM instance of 64 kbits, the power consumption is a mere 9 uA/Mhz and leakage in power-down mode is 0.91 uA.
More information on http://www.dolphin.fr/flip/ragtime/65/ragtime_65_ram.html
|
Dolphin Design Hot IP
Related News
- DOLPHIN Integration releases a ROM in 65 nm with Ultra high density and ultra low leakage
- Dolphin Integration offers first standard cell library to enable a leakage reduction of 1/350 at 65 and 55 nm
- Dolphin Integration announces the availability of a flexible CODEC configuration with ultra low power for providing Nomad systems
- Dolphin Integration releases its RAM for 90 nm nodes with dual optimization: for ultra-low power and for extremely high density
- INGChips selects Dolphin Integration's Power Management IP Platform for its ultra Low Power Bluetooth Low-Energy SoC in 40 nm eFlash
Breaking News
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Leveraging Cryogenics and Photonics for Quantum Computing
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
- Credo at TSMC 2024 North America Technology Symposium
- Cadence Reports First Quarter 2024 Financial Results
Most Popular
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
- Silicon Creations Reaches Milestone of 10 Million Wafers in Production with TSMC
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- Alphawave Semi: FY 2023 and 2024 YTD Trading Update and Notice of Results
E-mail This Article | Printer-Friendly Page |