Averant and AerieLogic to Ease the Usage of Formal Property Verification

Formal-VIPs integration with Solidify automates OCP Protocol Exhaustive Verification

San Jose, Calif. and Hérouville-St-Clair, France -- December 17, 2007 – Averant Inc., a leading provider of advanced verification technology for RTL design and AerieLogic s.a.r.l., a company expert in assertionbased verification today jointly announced the immediate availability of AerieLogic's Formal Verification IPs integrated with Averant's high capacity formal property checker Solidify.

Formal-VIPs automatically and exhaustively prove that your design is 100% compliant with busprotocols, without any knowledge needed in assertions or formal verification. Associated to the Solidify high capacity formal property checker, Averant's users can automatically and quickly prove compliance of their designs against popular protocols such as OCP 2.2, and reuse the Formal-VIP environment for their own properties written in SVA, PSL or HPL.

Formal Property Checking is a powerful Assertion-based Verification (ABV) approach to functional verification of digital circuits. It will exhaustively verify that a set of assertions holds on a design or compute counter-examples automatically. Implementing this methodology involves a training ramp-up, which becomes a barrier to deployment of this technology.

Formal-VIPs are verification IPs specifically developed for formal property checkers. They provide a widely automated flow, including graphical wizard, inline help and syntax/semantic checks, to configure the IP in accordance to the design's protocol features, to create a complete formal verification environment, and to instantiate all assertions to fulfill 100% compliance. No knowledge of assertion languages or formal verification is needed to use a Formal-VIP. Formal-VIPs can also be used in simulation for complementary functional verification.

Solidify is the state of the art in static functional verification. The underlying technology is very mature, having been employed on countless production designs. Solidify is feature-rich, powerful, and flexible, allows use by both designers and verification engineers, and adapts easily to any environment. It offers capabilities for both novice and expert users, and interfaces to other programs such as simulators and debuggers.

The integration of Formal-VIPs with Solidify provides Averant's customers with a fully automated path for 100% compliance against popular bus-protocols such as OCP 2.2/2.1/2.0, OCP 1.0 or OCP Sonics2.4. "Formal-VIPs help the adoption of formal property checking. We are happy to provide Averant's customers with a powerful and easy solution for exhaustive protocol checking" says Samuel Dellacherie, CEO of AerieLogic. “Our customers have been telling us that unavailability of formal VIP’s is a major barrier to wider deployment of formal technology” says Ramin Hojati, President of Averant. “This integration opens the door to a whole new era in formal verification, where customers are able to use third party verification IP’s with their formal tools.”

Availability

Solidify 4.0, tested in this integration, is available on Linux, Solaris, and Windows operating systems. Formal-VIPs targeting OCP 2.2/2.1/2.0, OCP 1.0 and OCP Sonics2.4 are available for Solidify on Linux and Solaris platforms.

About Averant

Averant Inc., founded in 1997, is a privately held EDA firm pioneering new methodology and technologies for static formal verification. Averant's flagship product is Solidify, a robust formal verification engine that provides the basis for property-based design verification, protocol verification, timing constraint verification, and automatic design checks -- all without the need for simulators or test vectors. These tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, see our web site at www.averant.com.

About AerieLogic

AerieLogic is a French start-up company based in Normandy that was created in 2005 by a team of experienced engineers in Assertion-based Verification (ABV) and in Formal Verification. The company's goal is to enhance the SoC functional verification flow using an assertion-based methodology (ABV) and formal verification. These technologies are difficult to bring into action, and AerieLogic leverages it's team extensive experience to provide automated formal solutions that enable non-expert users to take full advantage of assertions and formal verification. For more information, please visit our site at www.aerielogic.com.