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Industry Collaboration For DDR Memory System Development Joined by LSI and STMicroelectronics
Expanded Working Group to Deliver Next Version of DDR PHY Specification Minimizing Design and Integration Cost Benefits with Reusable IP SUNNYVALE, Calif., July 23, 2008 – Denali Software, Inc., today, as one of the DDR PHY Interface (DFI) specification participating members including ARM, Denali, Intel, and Samsung, announced that LSI Corporation and STMicroelectronics have joined the collaborative technical working group for the industry standard DDR-PHY Interface (DFI) specification, which simplifies the interoperability between the memory controller and PHY. Representatives from these industry-leading companies make up the collaborative technical working group, which plan to contribute to improvements and enhancements in the next version of the DFI specification. With the expanded technical working group, including LSI and STMicroelectronics, the ongoing development of the specification will continue to benefit PHY providers, chip architects and memory controller vendors, speeding their DDR memory system design and integration, reducing significant verification costs. “Industry-accepted interface specifications simplify development and facilitate interoperability,” said Don Friedberg, director of Foundation IP Solutions at LSI Corporation. “The DDR-PHY Interface specification will help streamline the integration of memory interface PHYs with high-performance controllers.” “STMicroelectronics is a strong promoter of open industry standards. Parallel DRAM interfaces are increasingly becoming a performance driver for many of our system-on-chip products in computer peripheral, consumer, telecom, and wireless applications,” said Pierre Dautriche, AMS and PHY IPs director at STMicroelectronics. “It is therefore natural that ST joins the DFI standardization body, which will benefit our customers with higher performance in our DDR interfaces.” This current version of the specification, DFI 2.0, available through a click-thru license at: www.ddr-phy.org, supports DDR1, DDR2, Mobile, and DDR3 memory; adds read, write, and gate training interfaces; and improves upon the interoperability features between the memory controller and a DDR PHY. The official version of the specification has been based on the 1.0 foundation of the common interface between DDR-DRAM memory controller logic designs and DDR DRAM physical interface (DDR PHY) designs. This specification allows designers a standard that has wide industry acceptance and ensures that the controller and PHY will work optimally together and no changes will be required to the hardened logic, resulting in reduced cost, time-to-market, and increasing reusable system IP. Further DDR DRAM and PHY technical discussions, presentations, and supporting technologies will be highlighted during the upcoming MemCon event, “The Technology Roadmap for Memory and Storage,” in Santa Clara, CA., from July 21-24. “LSI and STMicroelectronics coming aboard as technical contributors to the next DFI specification represent the significant awareness and the importance of a standard interface between the controller and PHY,” said Bryan Jones, who oversees Corporate External IP Management for Intel’s Mobility Group. “Amidst the growing community of technology experts and interface users, the contributions from the expanded technical team will increase further industry adoption, technical advancement, and exciting opportunities.” “With these new additions to the contributing technical committee, we look forward to improvements in the next version of the existing specification,” said Brian Gardner, vice president of IP products at Denali. “The industry will continue to benefit from memory controllers and PHYs that fall in line with the specification, providing enhanced interoperability and high performance.” About the DFI Specification The DDR PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices. For more information about the DFI specification, visit: www.ddr-phy.org. About Denali Software Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry’s most trusted solutions and platforms for deploying PCI Express®, NAND Flash and DDR DRAM subsystems. Developers use Denali’s EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products, and services is available at www.denali.com.
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