Reading Cadence's tea leaves
(11/30/2008 4:34 PM EST)
Analysis of what might be Cadence next step.
Being a large and until recently successful company has its disadvantages: one is being in the News a lot. And so Cadence is now going through the type of experience a successful company that has hit a few hurdles is bound to endure. This is particularly evident this time of the year, when product announcements and even hard news are few. Recently the News was once again dominated by Cadence. We learned that three of their people had been promoted to executive management, that the NASDAQ had warned the company that it was not in compliance with its rules, and that a number of companies had been "booted" from its Connections program. Taken together they created a confusing picture, at least at first look.
What I find intriguing is the reason for this apparent lack of direction. Since the resignation of Mike Fister, whether voluntary or forced may be irrelevant, the company seems adrift, taking decisions that seem disconnected and short term. Clearly the "Office of the Chief Executive" is a short term position, since a triumvirate cannot govern effectively for very long, destined to be replaced by a real Chief Executive when one is found.
Then came the very predictable "cut in costs" activity. Cutting costs is an action that is meant to signify that executive management has both a grip on reality and an understanding of the business reality. As a mater of fact, cutting 10% out of almost 7000 employees, is relatively easy to do, although the after shocks are difficult to manage.
E-mail This Article | Printer-Friendly Page |
Related News
- Reading the tea leaves: How deep will EDA losses go?
- Intel and Cadence Expand Partnership to Enable Best-in-Class SoC Design on Intel's Advanced Processes
- Cadence Unveils Millennium Platform - Industry's First Accelerated Digital Twin Delivering Unprecedented Performance and Energy Efficiency
- Cadence Unveils New Palladium Z2 Apps with Industry's First 4-State Emulation and Mixed-Signal Modeling to Accelerate SoC Verification
- Cadence Signoff Solutions Empower Samsung Foundry's Breakthrough Success on 5G Networking SoC Design
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- SEMIFIVE Starts Mass Production of its 14nm AI Inference SoC Platform based Product
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024