Digital Core Design introduces Local Interconnect Network IP Core
Bytom -- January 31, 2013 -- The DLIN is the newest Local Interconnect Network IP Core developed by Digital Core Design. Polish IP Core provider has presented a solution, which is fully compatible with the LIN 1.3, 2.1 and the newest version 2.2 Revision A, released by the LIN Consortium.
The core is described at RTL level, empowering the target use in both, FPGA and ASIC technologies.
“Our DLIN controller supports transmission speed between 1 and 20kb/s that allows to transmit and receive LIN messages compatible to LIN 1.3, LIN 2.1 and also the newest LIN 2.2 rev A”
Jacek Hanke, CEO, Digital Core Design
The DLIN, DCDs IP Core for Local Interconnect Network, is an ideal solution most of all for automotive designs. As technologies and facilities implemented in a car grow every year, the need for a cheap serial network has arisen. Thats why LIN seems to be the most suit-able solution to integrate intelligent sensor devices or actuators in todays cars. Contrary to the CAN, it enables cost competitive serial communication, building the same an extended vehicles electrical network, which
will be used as CANs sub-network. Our DLIN controller supports transmission speed between 1 and 20kb/s says Jacek Hanke, CEO in Digital Core Design that allows to transmit and receive LIN messages compatible to LIN 1.3, LIN 2.1 and also the newest LIN 2.2 rev A.
Compared to the CAN, LIN is slower, but thanks to its simplicity, it is much more cost effective. Thats why the DLIN is ideal for communication in intelligent sensors and actuators, where the bandwidth and versatility of CAN is not required. DCDs IP Core provides an interface between a microproces-sor/microcontroller and a LIN bus. It can work as a master or as a slave LIN node, depending on a working mode determined by the microprocessor/microcontroller. The reported information status includes the type and condition of transfer operations being performed by the DLIN, as well as a wide range of LIN error conditions (overrun, framing, parity, timeout). DCDs IP Core includes also a pro-grammable timer, which allows to detect timeout and synchronization error. The Core is described at RTL level, empowering the target use in FPGA and ASIC technologies.
More information & data sheet: http://www.dcd.pl/ipcore/132/dlin/
- Conforms with LIN 1.2, LIN 2.1 and LIN 2.2 specification.
- Automatic LIN Header handling
- Automatic Re-synchronization
- Data rate between 1Kbit/s and 20 Kbit/s
- Master and Slave work mode
- Time-out detection
- Extended error detection
- Break-in-data support
- Available system interface wrappers:
- AMBA - APB Bus
- Altera Avalon Bus
- Xilinx OPB Bus
Contact Digital Core Design