Palmchip Introduces New AcurX Series of Configurable System-On-Chip Platforms for Mega-gate Chip Designs

• AcurX features Palmchip's new Matrix™ technology for increased bandwidth, plus multi-processor and multi-memory subsystem support for greater flexibility and increased system performance
• CrosSwitch™ on-chip networking simplifies mega-gate design and layout
• Timing Taps™ technology corrects interconnect timing even after layout without going back through design

SAN JOSE, California, October 28, 2002 – Palmchip Corporation today announced its new AcurX configurable SoC (system-on-chip) platform aimed at increasing design flexibility and overall system performance for any digital design of three million gates and above. The new AcurX, a highly integrated, configurable, pre-verified platform, enables the designer to support multiple CPU cores in a single design. The patent-pending Matrix technology enables designers to incorporate multiple memory subsystems, each optimized for specific data requirements. The AcurX platform provides over three times the available bandwidth of previous platforms through the use of the Matrix technology and on-chip SRAM. Applications achieve the maximum throughput by simultaneously accessing the different memory subsystems. This powerful combination provides high data availability for DMA scatter-gather descriptors, secure memory for encryption, and fast accesses for application stacks.

To address the issues of routing large chips, Palmchip is introducing the new patent-pending CrosSwitch technology as part of the AcurX platform. Instead of being a point-to-point connection, CrosSwitch technology uses nodes that allow a data source to connect to multiple on-chip cores. The nodes localize routing complexity, resulting in reduced wiring congestion and routing time.

With the release of the AcurX SoC platform, Palmchip is also introducing the new patent-pending Timing Taps technology. As more functionality is brought on-chip and designs continue to grow larger, surpassing the three million-gate threshold, re-working the interconnect timings can take months to meet the original design specification resulting in unplanned design iterations. Now, designers can easily tap into an on-chip bus, insert a Timing Tap, and correct the interconnect timing. This can be done at any stage of the design process even after layout has been completed, without ever having to go back through the design stage.

"AcurX is the result of an 18 month-long effort to develop a product and underlying technology to address the growing requirements of mega-gate SOC designs, " said Jauher Zaidi, president and CEO of Palmchip Corporation. "By providing a pre-verified SoC platform with this new technology, our customers are able to implement complex designs today and plan for future design growth without having to change the basic platform foundation."

Palmchip's SoC platforms products have been used to build chips for many applications including cell phones, a single chip DVD player, smart card, digital still camera, networking devices and disk drives. The architecture of the AcurX platform allows for the easy integration of Palmchip's IP technology as well as third-party IP cores. Palmchip provides customers the option of securing their application's IP and integrating it with the SoC platform; or Palmchip can secure IP and provide a single license that covers the entire application SoC, saving the customer the burden of IP evaluation, and managing multiple licensing agreements.

The AcurX SoC platform product comes complete with a CPU bridge, memory subsystems, DMA controllers, power management, an interrupt controller, watchdog and general-purpose timers, two UARTs, I2C and SPI masters, and a real-time clock. Other peripheral cores, including IDE host, master-slave PCI and PCMCIA are also available pre-integrated in the platform. The AcurX platform is delivered with Verilog RTL code, synthesis scripts for Artisan's TSMC 0.18-micron library, a platform test bench, test suite, simulation models, and user's manual. The platform can be targeted to any number of foundries. AcurX currently supports MIPS4K series, ARC, ARM7TDMI, and ARM9TDMI embedded processor cores. Boot code and API software is available for any of these processors. The platform architecture is inherently processor independent, allowing other processors to be easily integrated, including PowerPC, and Tensilica. The platform is suitable for use as an embedded device, or as a companion chip for high performance processor chips, such as the Strong ARM SA1100, and PMC-Sierra RM7000 processors.

Based on the customer's requirements, an AcurX platform can be configured in approximately an hour to create a top-level chip. Using Palmchip's SurfBoardÔ SoC development platform, the customer can then download the chip and immediately begin software development.

Availability
AcurX is available today. Contact Palmchip Corporation for pricing. 408-952-2007

About Palmchip
Palmchip Corporation develops and licenses configurable SoC platforms, subsystems, and IP cores for embedded SoC's used in a variety of applications. Palmchip's IP is based on its CoreFrame®integration technology. This technology is independent of processor, I/O or foundry, allowing designers flexibility in porting IP from any number of sources. Palmchip was established in 1996 and is today a privately held company based in San Jose, California (USA). More information can be obtained at www.palmchip.com.

Palmchip, the palm leaf logo and CoreFrame are registered trademarks of Palmchip Corporation. AcurX, Matrix, Timing Taps, and CrosSwitch are trademark of Palmchip Corporation. All other trademarks are the property of their respective owners

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