Pioneering DSP core breaks more ground with new processing modules

Math-intensive introductions strengthen applications for novel adaptive-datapath data engine in audio, wireless and control

Cambridge, UK, September 3, 2004 --- Cambridge Consultants has extended the versatility of its ground-breaking adaptive-datapath DSP core - APE2 - with new processing modules for math-intensive embedded applications. These ready-to-use modules facilitate the rapid development of highly-efficient signal-processing data engines for ASIC applications in consumer markets such as wireless, audio and control.

Conceived just three years ago, APE2 has enjoyed successful implementation in many cost-sensitive applications including high volume consumer devices, professional radio systems and industrial automation and control. As an example of the core's potential for catalysing new products, a configuration for a hearing aid application required less than 20,000 gates, and was implemented on a die size of less than 0.5mm2 using 0.18µm CMOS geometry, with a power consumption of under 50µW.

APE2's very long instruction word (VLIW) architecture features a novel parallel structure with processing modules such as single-cycle MACs and ALUs connected to a common data routing bus. Designers configure the DSP for the application by choosing the appropriate processing module functions and quantities from the library, and configuring the width of the data bus in increments as small as one bit at a time.

Performance is optimised by means of dynamic datapath routing - which allows the output of any processing module to be made available at the input of any other. This innovative feature allows designers to create dedicated computational structures for each instruction or subroutine - and perform multiple operations in parallel - effectively providing dynamic hardware reconfiguration. For example, a DSP's arithmetic modules might be connected in a wide parallel structure to rapidly process audio data, and then reconfigured to handle smaller data widths such as sensor inputs at a later stage of an algorithm.

The extensions to the APE2 DSP core's module library provide ready-to-use circuit configurations for a range of math-intensive signal processing tasks. The new options include: sin/cos/tan/arcsin/arccos and arctan calculation; vector magnitude; ratios and reciprocals; coordinate transforms; and square root, exponents and logarithms. These blocks join APE2's existing processing modules, which include MAC, ALU, radix-4 FFT, sequencing, I/O registers, and memory interfaces.

Using combinations of these resources, developers can configure powerful data engines for executing the algorithms required in a wide range of consumer applications. Examples include executing linear algebra for real-time control, processing the compression formats used by digital music files, and implementing signal processing functions such as adaptive filters and down-converters in wireless systems.

"Most commercial DSP intellectual property is targeted at high-end applications and is difficult to cost-justify for cost-sensitive volume products, forcing companies to develop dedicated hardware," says Richard Traherne of Cambridge Consultants. "APE2's blend of compactness and customizable performance feeds the burgeoning demand in the low to medium-end embedded DSP space, providing similar performance to dedicated logic, but in a much more versatile and programmable form. It's also offered with a royalty-free license, providing ideal support for OEMs targeting consumer markets."

Monty Barlow, who leads Cambridge Consultants’ Digital Signal Processing Group adds "The dual level of optimization stemming from APE2's dynamic datapath routing and hardware configurability gives designers enormous latitude to implement powerful application-specific signal processing and control algorithms using tiny amounts of silicon. Moreover, the dynamic datapath routing gives OEMs freedom throughout the design cycle to modify designs to accommodate changing requirements."

A powerful toolkit is provided to APE2 licensees, supporting hardware selection, code generation for any hardware configuration, design optimization including code compression, and software simulation. The tools automatically generate Verilog source code including ROM decompression hardware. The tools provide users with complete control and flexibility over their DSP design. Cambridge Consultants also offers a ready-integrated combination of the DSP with the XAP RISC processor core family, providing a time saving solution for single-chip applications involving data-intensive processes. Unlike many cores on the market, both the DSP and RISC processor designs are available with royalty-free licenses.

The functional flexibility opened up by the configurability of the DSP hardware and the data routing bus gives product designers considerable latitude to exploit APE2 to reduce NRE (non recurring engineering) costs for products requiring different capabilities for different markets. One DSP core design could be programmed to support different wireless data modulation schemes for example.

Alternatively, a developer can use the optimization facilities built into the tool suite to make APE2 designs as economic as possible, by identifying unused or seldom used resources, and eliminating these to make the design highly application specific.

Details of the core are available at: www.CambridgeConsultants.com/ASIC.