Top Story
PLDA, the industry leader in the high-speed bus IP market, today announced that Great River Technology has licensed PLDA’s EZ DMA IP core for Xilinx® 65nm Virtex™-5 FPGAs. The PLDA core will be integrated into Great River Technology’s MATRIX PCIe4 high speed ARINC 818 video card for the avionics industry.
Top Story
This technology initiative includes the development of new memory signaling innovations that will facilitate blazing fast data rates of 16Gbps and enable a future memory architecture that can deliver an unprecedented terabyte per second (TB/s) of memory bandwidth (1 terabyte = 1,024 gigabytes) to a single System-on-Chip (SoC)
Top Story
Faraday today launched the ARM v5 instruction set architecture (ISA) compliant processor - FA606TE, which is an ultra low power 32-bit RISC with the synthesizable and configurable features
Top Story
The DesignWare Wireless USB Device IP is designed to the WiMedia Alliance Ultra-wideband (UWB) Common Radio Platform and includes a WiMedia MAC-PHY interface for interoperability with WiMedia UWB PHYs such as those from Alereon and Realtek
Top Story
The Platform Baseboard for the ARM11 MPCore multiprocessor is especially designed for symmetric multiprocessing applications development at near real time speed. It consists of a test chip ASIC containing four ARM11 MPCore multiprocessors and Level2 cache running at 200 Megahertz, and a memory system on a structured ASIC containing all the speed critical peripherals commonly seen in embedded systems running at 100 Megahertz.
Top Story
ARC International today announced an optimized MP3 decoder for its ARC® Sound Subsystem operating at under 7 MHz and dissipating less than 0.46 mW of power in a TSMC 90 G process.
Top Story
Addressing the burgeoning Bluetooth market, the combined reference design integrates ROHM's 2.0+EDR Radio with CEVA's Bluetooth 2.0+EDR baseband and protocol stack IP for a high-performance, low-power Bluetooth 2.0+EDR platform.
Top Story
The MoSys SATA GEN II (3.0Gbs) PHY IP is compliant with Serial ATA II Electrical Specification Revision 2.5 and is backward compatible to the widely deployed Gen I (1.5GbS) Serial ATA standard.
Top Story
SonicsExpress enables developers to extend the globally asynchronous locally synchronous (GALS) capabilities of Sonics SMART Interconnect solutions, while maintaining automated system level verification and ultra-low power consumption.
Top Story
Anchored by an enhanced 32-128 bit Processor Local Bus (PLB) the platform delivers increased performance and scalability for future performance and feature requirements from Xilinx. The MicroBlaze(TM) 32-bit processor now includes the industry's only configurable Memory Management Unit (MMU) that enables commercial-grade operating system (OS) support and is supported by a host of upgraded IP and design tools delivered with the Embedded Development Kit (EDK) version 9.2.
Top Story
Silicon Hive announces the HiveFlex VSP 2500 Video Signal Processing solution for Full High Definition (HD) video codecs. It is the world’s first fully-programmable video coding solution for Full HD (1080p).
Top Story
The Menta’s eFPGA IP is a customizable domain-specific programmable core made with dedicated Look-Up-Tables (LUT), and according to the targeted applications, some additional hard macro blocks (multiplier, memory…) can be plugged inside the core to increase speed, reduce power and area.
Top Story
Rambus Inc., one of the world's premier technology licensing companies specializing in high-speed memory architectures, has signed a memorandum of understanding with Intel to explore possible uses for Rambus' family of XDR™ memory solutions.
Top Story
Microtronix® today announced the launch of the Video LVDS SerDes Transmitter / Receiver IP Core targeted at the burgeoning high resolution 1080p 100/120 LCD panel display systems.
Top Story
VeriSilicon Holdings Co., Ltd., a System-on-A-Chip (SoC) platform based integrated circuit design foundry, today announced that it raised US$20 million in its Series D financing, bringing the total amount of venture funding received to US$58 million since the company's inception in 2001.
Top Story
Synopsys today announced that PMC-Sierra was able to achieve first-pass silicon success for their high-performance design using Synopsys' DesignWare® Bridge IP for PCI Express 2.0 (Gen II) to ARM® AMBA® 3 AXI(TM) and the DesignWare interconnect fabric for AMBA 3 AXI. The DesignWare Bridge IP for PCI Express 2.0 to AMBA 3 AXI operating at 5.0 Gbps, is the first PCI Express 2.0 IP solution to achieve silicon success.
Top Story
The AFE platform consists of a dual matched ADC (IQ-ADC), dual matched DAC (IQ-DAC), an auxiliary ADC and DAC for monitoring and control, and a versatile PLL, suitable for portable mobile applications. At low power levels for the receive channel, and with a fast wake-up from standby, it helps extend battery life in portable applications.
Top Story
Eureka Technology today announces the immediate availability of SD/SDIO/MMC slave controller core that supports Secure Digital (SD) and Multi-Media Card (MMC). Eureka has provided SD and MMC IP cores to many licensees since 2004. This latest addition of the slave controller completes the product line. A hardware development board for SD/SDIO/MMC development will also be available soon.
Talk to us
Add your Products