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How to Design Cost–Optimized Embedded System with ARM926EJTM Embedded System designers now have an alternative for developing optimized and affordable systems that are customizable in both hardware and software. eASIC’s Nextreme Structured ASICs provide you with the benefits of zero mask-charges, no minimum order, and 3-4 weeks turnaround. Our IP portfolio, including 150MHz soft ARM926EJTM processor, can help you build low-cost customized embedded system. Download White Paper by ARM and eASIC

Design Platform / Structured ASIC News

• eASIC and IPextreme Announce Freescale ColdFire Processors for Nextreme NEW ASICs (Jun. 16, 2009)
  eASIC and IPextreme today announced the immediate availability of Freescale’s 32-bit V1 and V2 ColdFire processor cores for Nextreme NEW ASICs.
  
  
• eASIC Accelerates DSP Market Momentum with New IP cores (May. 07, 2009)
  eASIC today announced the immediate availability of two new DSP IP cores, an FFT and FIR Filter Compiler, to accelerate it’s growing momentum into the high performance DSP market. The new FFT core, available from eASIC, supports point sizes from 16 to 16K points and data rates up to 100 MSPS with a compact footprint.
  
  
• Triad Semiconductor Introduces Mocha Family to Extend Via-Configurable Array Benefits to Mixed-Signal ASIC Design (Mar. 02, 2009)
  Triad Semiconductor today introduced a new family of ARM Powered® VCAs (via-configurable arrays) that combine the recently announced ARM® Cortex™-M0 processor with Triad’s silicon-proven analog, digital and memory building blocks on an array that can be configured by changing a single via layer.
  
  
• ChipX Adds More Than 60 Analog Functions to IP Portfolio (Sep. 15, 2008)
  The ChipX analog building block catalog consists of many general purpose functions, available in 250nm, 180nm and 130nm processes. Building blocks include analog switches and multiplexers, charge pumps, comparators, self-calibrated termination, reference resistors, reference voltage and reference current generators, oscillator circuits, power-on-reset generators, operational amplifiers and various I/Os including HSTL, SSTL 1.5/1.8/2.5/3.3, LVPECL and LVDS.
  
  
• eASIC Delivers 45nm Zero Mask-Charge New ASIC Family (Aug. 04, 2008)
  Leveraging the rapid success of its award winning 90nm Nextreme ASIC Products, eASIC Corporation today announced its next generation Nextreme-2 Family – the semiconductor industry’s first 45nm, zero mask-charge New ASIC family.
  
  
• OmniVision and eASIC Offer MPEG-4 Reference Design to Provide Rapid Development of Camera Solutions (Jul. 31, 2008)
  The eDVR91, a camera reference design based on OmniVision's OV7725 CameraChip(TM) sensor and eASIC's eDV9100 MPEG-4 CODEC, enables the capture, compression and storage of digital video and audio on a Secure Digital (SD) storage card.
  
  
• eASIC Announces eDiVeo Family of Low-Cost Single-Chip Audio and Video Codecs (Jul. 17, 2008)
  Configurable Architecture Permits Rapid Deployment of Audio and Video Codec ICs Supporting MPEG-4, JPEG and H.264 Standards
  
  
• eASIC Enables Nexus Chips to Reduce Power Consumption by 80% Over FPGAs (Jul. 09, 2008)
  eASIC’s Zero Mask-Charge ASIC Devices Enable Nexus Chips to Increase Performance by 2X and Reduce FPGA Power Consumption by 80% for 3D Video Applications
  
  
• ChipX Strengthens Video and Wireless ASIC Capability With Addition of 10-Bit, 210Msps Digital to Analog Converter (DAC) Family to IP Portfolio (Jun. 30, 2008)
  Designed for high speed applications, the single, dual, triple and multi-channel ChipX DACs are ideal for system-chip designs used in component (RGB) or composite video encoding, WiMAX or 802.11 front-ends, and a variety of medical and industrial products
  
  
• eASIC zooms past 100th (Jun. 02, 2008)
  eASIC today announced that it has surpassed 100 design wins in only 18 months for it’s Nextreme family of 90nm ASIC devices.
  
  
• ChipX Introduces Synthesizable 32-Bit CPU With Best-in-Class Code Density for Embedded and Consumer Applications (Jun. 02, 2008)
  ChipX today announced the addition of the BA22, a 32-bit synthesizable processor with the highest code density available, to its extensive line-up of mixed-signal and synthesizable IP.
  
  
• Cypress Unveils Online Solutions Library of IP To Facilitate Faster, More Efficient PSoC Designs (May. 07, 2008)
  The new Cypress Solutions Library website is a free resource of user-generated IP that can be easily replicated for quick, effective design with Cypress's flexible, programmable PSoC® architecture, as well as for designs using Cypress's USB and proprietary 2.4-GHz WirelessUSB™ technologies.
  
  
• eASIC Shatters FPGA Performance With 235MHz LEON3 Processor (Apr. 17, 2008)
  eASIC and Gaisler Research migrated the LEON3 processor to eASIC’s Nextreme family of zero mask-charge ASIC devices and achieved 235MHz performance, shattering the performance achievable using high performance FPGAs
  
  
• ViASIC Technology Enables First Proven Two-Week Turnaround from Tapeout to Production for ASICs (Mar. 26, 2008)
  Sandia National Laboratories demonstrated this rapid turn-around for radiation-hardened (rad-hard) designs, using its ViArray trusted structured ASIC implementation platform based on ViASIC’s patented standard metal configurable fabric and Sandia’s radiation-hardened technology.
  
  
• eASIC Enables AVTECH to Reduce IP Surveillance Camera Cost by 45% (Mar. 25, 2008)
  The Nextreme device consolidated multiple high-performance image processing functions and enabled AVTECH to increase the camera features while significantly reducing overall system cost and power consumption.
  
  
• eASIC Corporation Announces a Landmark Program Aimed at Ushering in an Era of Affordable Silicon Customization (Mar. 18, 2008)
  The initial targets of this FPGA cost reduction program are the low density FPGAs that are primarily used in consumer and multimedia applications.
  
  
• ON Semiconductor Delivers Structured ASIC Technology for Military and Aerospace SoCs and FPGA-to-ASIC Conversions (Mar. 18, 2008)
  ON Semiconductor has announced that XPressArray-II (XPA-II), a leading structured ASIC technology formerly offered by AMI Semiconductor, is now available for military specification operating temperatures (as the M-XPA-II Family).
  
  
• ChipX Simplifies DDR2 Design With Industry Standard DDR PHY Interface v2.0 (Mar. 12, 2008)
  Targeted initially at the company's highly successful 130-nm mixed-signal offering, the new DDR/DDR2 controllers and PHY promise to dramatically simplify the development of high performance, mixed-signal ASICs.
  
  
• ChipX Achieves PCI Express Compliance Certification (Jan. 15, 2008)
  ChipX offers PCI Express solutions consisting of silicon proven controller and PHY that can be integrated in a mixed signal Standard Cell ASIC, Hybrid ASIC, Embedded Array, or Structured ASIC platform.
  
  
• ChipX Slashes Cost of System-on-Chip Development With Hybrid ASIC (Dec. 18, 2007)
  ChipX today announced the introduction of Hybrid ASIC, the implementation of a structured ASIC as IP on a Standard Cell device. This development approach allows for rapid and economical product line development, saving companies an average of three-to-five hundred thousand dollars in non-recurring engineering (NRE) and tooling costs and enabling them to introduce derivative products two-to-three months faster than today's methodologies allow.
  
  
• Arrow Electronics and Triad Semiconductor Team to Offer Mixed-Signal Via-Configurable Array ASICs (Dec. 10, 2007)
  Arrow will provide technical sales and support and product logistics for Triad’s mixed-signal ASIC customers. Triad’s patent-pending approach significantly reduces engineering labor and fabrication costs for high-performance ASIC designs, and can speed “time-to-prototype” by more than half a year.
  
  
• eASIC and Tensilica Partnership Delivers Free Diamond Processors on Free Mask Charge ASICs (Nov. 26, 2007)
  Through this partnership eASIC now provides free access to Tensilica’s Diamond Standard microprocessor and digital signal processing (DSP) cores for its free mask charge, no-minimum order ASICs.
  
  
• QuickLogic Expands Into Mobile Accessory Market With SDIO Client System Block (Oct. 15, 2007)
  Part of QuickLogic's functional library for its Customer Specific Standard Product (CSSP) platforms, the new SDIO function enables a range of unique accessories for mobile devices utilising the popular SD memory card and SDIO peripheral interface.
  
  
• Atmel and Barco Silex Announce Collaboration for Systems-on-Chip based on Atmel's AT91CAP Customizable Microcontroller (Sep. 11, 2007)
  Atmel and Barco Silex announced today an extension of their long-standing collaboration to develop systems-on-chip for their mutual clients, based on Atmel’s CAP™ ARM®-based customizable microcontroller, with design expertise and European customer support from Barco Silex.
  
  
• Atmel and Lead Tech Design Collaborate for Video Systems-on-Chip based on Atmel's AT91CAP Customizable Microcontroller (Sep. 06, 2007)
  Atmel® Corporation and Lead Tech Design (LTD) announced today a collaboration to develop video systems-on-chip, based on Atmel's AT91CAP customizable microcontroller for their mutual clients, with video expertise and hardware and software IP blocks contributed by Lead Tech Design.
  
  
• QuickLogic Extends CSSP Library With Bluetooth 2.1 + EDR Compatible High Speed UART Core (Sep. 06, 2007)
  With the advent of Bluetooth 2.0/2.1 and its EDR transfer mode for highspeed streaming, UARTs traditionally used in mobile application processors are proving to be too slow. The new UART system block from QuickLogic offers the level of performance that Bluetooth 2.1 + EDR requires.
  
  
• Triad announces availability of its new LVDS Transmitter and Receiver drivers (Sep. 03, 2007)
  These drivers can be used in such applications as; High Speed Backplane Driver, Complementary Clock Drivers, Level Translator, System Interconnects, ATM Applications, SDH Applications, High-Resolution Imaging Applications, Laser Printers, Digital Copiers, Stackable hubs for data communications, Digital Video, and High Definition Television.
  
  
• ChipX XPath Methodology Enables Seamless Migration from Structured ASIC to Standard Cell (Aug. 22, 2007)
  The methodology, called XPath, enables customers to get products to market quickly and inexpensively and will play a valued role in the production of ASICs for a wide variety of applications, including consumer electronics and embedded products.
  
  
• QuickLogic Announces Availability of Ultra-Secure, Digital Rights Management, Single-Chip Silicon Solutions for Handheld Electronics Products (Aug. 20, 2007)
  QuickLogic today announced it has added a suite of digital rights management (DRM) security functions, including AES encryption, to the library of IP available for its programmable connectivity platforms. The technology greatly enhances time to market and time in market for handheld elec tronics products. It allows developers to extend the capability of their chosen embedded systems processor with both the security and peripheral interfaces they need, via a single low power consumption IC.
  
  
• eASIC and Avnet ASIC Israel (AAI) Partner to Support Increasing Demand for Structured ASICs in Israel (Aug. 08, 2007)
  The partnership agreement will enable AAI to offer low-power, low-cost (zero mask cost) and short turnaround 90nm Structured ASICs. Under the agreement, AAI will provide design, technical and sales support to customers using eASIC’s products in Israel.