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China readies first multicore Godson CPUs (Aug. 28, 2008)
Chinese researchers are preparing the first multicore versions of Godson, the country's first homegrown microprocessor, with a four- and eight-core designs scheduled to tape out in the coming months. China hopes to build a petaflops high-performance computer based on the Godson-3 in 2010. |
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Fresco Logic Demonstrates Industry's First SuperSpeed USB Data Transfer (Aug. 21, 2008)
Demonstration Showcases SuperSpeed USB Data Transfer Speed of Over 350 MB/s on Fresco Logic's Hardware Development Platform |
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Arasan Chip Systems Reveals Strategic Mobile Initiative (Aug. 20, 2008)
This strategic initiative centers on 2 key areas: (1) Arasan's technology expertise in the mobile IP space and (2) an "Arasan driven IP eco-system" of partners and customers throughout the mobile market. |
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STMicroelectronics Demonstrates First Physical Layer IP For 6Gb/s SATA Hard Disk Drives (Aug. 19, 2008)
ST’s 6Gb/s SATA PHY is an IP (Intellectual Property) block designed to be integrated with other functions into low power System-on-Chip (SoC) devices supporting 1.5 and 3 Gb/s as well as 6 Gb/s SATA HDDs for mobile and desktop computing applications |
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IBM Builds World's Smallest SRAM Memory Cell (Aug. 18, 2008)
IBM and its joint development partners -- AMD, Freescale, STMicroelectronics, Toshiba and CNSE -- today announced the first working static random access memory (SRAM) for the 22 nanometer (nm) technology node. |
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ARM Mali-200 GPU Compliant With OpenGL ES 2.0, OpenGL ES 1.1 and OpenVG 1.0 (Aug. 15, 2008)
The ARM® Mali™-200 graphics processing unit (GPU) is compliant with the full range of Khronos embedded 2D and 3D graphics standards: OpenGL ES 2.0, OpenGL ES 1.1 and OpenVG 1.0. |
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POWERVR SGX First with Conformance for all Khronos Mobile APIs on Production Silicon (Aug. 15, 2008)
Imagination’s POWERVR MBX 3D acceleration core is also conformant with Khronos’ OpenVG 1.0.1 and OpenGL ES 1.1 APIs. |
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Synopsys Launches Full Range of Silicon-Proven DDR3 and DDR2 IP Solutions for SoC Designs (Aug. 13, 2008)
The DesignWare DDR IP solutions deliver memory system performance of up to 1600 Mbps, the maximum data-rate of the JEDEC DDR3 specification. The solutions include configurable protocol and memory controllers, integrated mixed-signal PHYs including I/Os and verification IP. |
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Crocus Establishes Prototyping Environment for Next Generation MRAM Technology (Aug. 12, 2008)
Crocus Technologies today announced that it has qualified its complete manufacturing environment for the development and rapid prototyping of MRAM. |
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Silvus Technologies and Ittiam Systems Announce Expanded Product Line and Commercial Availability of 802.11n IP Solution (Aug. 11, 2008)
Silvus Technologies and Ittiam Systems today announced the availability of an expanded line of PHY/MAC 802.11n IP solutions, which now covers multiple MIMO configurations (1x1, 2x2, 4x4). |
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MIPS Technologies Announces USB PHY Breakthroughs (Aug. 11, 2008)
MIPS Technologies today introduced the industry's first 40nm USB PHY IP core and first USB-certified 1.8v 45nm USB PHY IP core. |
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Cosmic Circuits Announces Validation as a Common Platform Solution Provider of New Analog IP Cores (Aug. 08, 2008)
Cosmic Circuits, a leading provider of differentiated Analog and Mixed-signal IP, today announced the validation of silicon IP cores for 90nm Common Platform™ technology. This includes IP cores for high-performance power-regulation and analog-to-digital conversion that are used predominantly in chips for portable consumer products and communications. |
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Great River Technology Releases ARINC 818 Video IP Core for Xilinx and Altera FPGAs (Aug. 07, 2008)
Great River Technology Releases ARINC 818 Video IP Core for Xilinx and Altera FPGAs
Great River Technology released the first ARINC 818 IP core for aerospace and military video applications. The IP core targets both Xilinx and Altera FPGAs and drastically reduces the effort of implementing an ARINC 818 interface into new applications. |
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CAST Offers Special System Library IP Package for AMBA-Based FPGAs and SoCs (Aug. 07, 2008)
CAST and SoC Solutions today announced that the complete PiP-AMBA system infrastructure library is now available in a special website-only package, with a simplified license for easy purchase, and a reduced US price of $10,000. |
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UMC's Embedded DRAM, URAM(TM) Proven in 65nm Customer Silicon (Aug. 04, 2008)
Pure-Play Foundry Industry's Only Proprietary Embedded DRAM Solution Enables Performance, Size and Cost Advantages for SoC Products |
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Evatronix announces T8051 - the world's smallest 8051 ISA-compliant IP Core. (Aug. 01, 2008)
A significant decrease in the number of gates does not affect performance, which surpasses the original MCU by more than 4 times. |
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Denali Announces Complete Bundle of I/O Virtualization Technology Solution With PureSpec PCI Express Verification IP (Jul. 31, 2008)
Industry-Leading Verification IP Solution Provides Full Specification Support Of PCI-SIG IOV Technology Standard |
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Denali Releases ONFi 2.0 Memory Controller and Verification Suites (Jul. 31, 2008)
FlashPoint Platform Supports ONFi 2.0 NAND Flash Technology for PCIe-based Memory Systems |
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Vivante Brings GPU IP Solutions to MIPS Alliance Program (Jul. 30, 2008)
Vivante will optimize its HD Visual Reality and Mobile Visual Reality line of 2D and 2D/3D graphics processor IP solutions, for integration in designs using the MIPS32® 24K® and MIPS32® 24KE™ cores, which are widely used in media server, DVD, set-top box and mobile solutions. |
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MOSAID to Unveil Enhanced Flash Architecture for Solid State Drives (Jul. 29, 2008)
MOSAID's HLNAND(TM) Flash is a new architecture and interface for high-performance Flash memory. |
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Vivante's OpenGL ES 2.0 Conformance Submission First to Support Depth Texture Extension (Jul. 28, 2008)
Vivante has submitted conformance results based on the GC600 2D/3D GPU IP core for the OpenGL ES 2.0 conformance test to the KhronosTM Group for review. |
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MIPS Technologies' Silicon-proven GPS RF Tuner IP Reduces Risk for Developers of Next-generation Devices with GPS (Jul. 28, 2008)
The silicon-proven, integrated low-noise RF front-end for GPS receivers in the L1 band enables embedded system designers to decrease costs and time-to-market for next-generation devices incorporating GPS. |
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Synopsys Announces Availability of New Fully Synthesizable PowerPC Cores (Jul. 23, 2008)
Synopsys today announced the availability of fully synthesizable implementations of the IBM PowerPC® 460 and cache configurable PowerPC 405 embedded microprocessor cores as components of the DesignWare® Star IP program. |
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DOLPHIN Integration launches the 32-bit challenger: FlipAPS-32, a processor tiny enough for embedding controls (Jul. 21, 2008)
Dolphin Integration and Cortus SA are partnering for this 32-bit processor with the silicon area of a 16-bit core and with a minimal power consumption, but with the largest addressing capability. |
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Denali Announces New LPDDR2 Memory Controller and PHY Solution (Jul. 21, 2008)
First Provider of Memory Controller and PHY Solution to Support LPDDR2 in Next-Generation Mobile and Embedded Applications |
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Algotronix adds thermal signaling to IP core DesignTag (Jul. 18, 2008)
Algotronix has added 'thermal signaling' to DesignTag, an active digital circuit element that can be designed-in to ICs and FPGAs and detected through-package by an external scanner. |
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eInfochips announces SPI4.2 and CCIR656 Stream Generator Design IP (Jul. 18, 2008)
eInfochips today announced the availability of OIF (Optical Internetworking forum) compliant SPI4.2 design IP (System packet interface Level 4 Phase 2) and ITU-R BT 601 and ITU-R BT 656 compliant CCIR 656 stream generator design IP. |
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Digital Blocks Announces I2C-Master Controller IP Core Family with the availability of the DB-I2C-M for the ARM AMBA 2.0 APB and Altera NIOS II Avalon Interconnects (Jul. 18, 2008)
The DB-I2C-M targets High-Performance Embedded Processor designs requiring a Smart I2C Controller in a small VLSI footprint |
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Athena Announces Cryptographic-Grade Random Number Generator (Jul. 15, 2008)
Portable to any semiconductor process, Athena's TeraFire RNG cores are a fast and reliable way to incorporate cryptographic-grade random numbers into your SoC design. |
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Synopsys Broadens DesignWare SATA Solution With Device IP (Jul. 14, 2008)
Comprehensive SATA IP Portfolio Including Device, Host, PHY and Verification IP Passes Interoperability Testing, Reducing Integration Risk for SoC Designs |
