Configurable PCI Express 2.0, 1.1 Controller IP for ASIC/SoC
[3739un] 10/8-bit, 2MSPS, 2.5V SAR ADC with 8:1 Differential Input Mux in UMC 65LL
USB2 nanoPHY, TSMC 55LP
USB 2.0 PHY IP core
Xilinx Achieves PCI Express Compliance Across its All Programmable 28nm Devices
Google TV Devices with Vivante GPU Cores Ready for Android Jelly Bean Update
Synopsys DesignWare IP for PCI Express 3.0 Passes First PCI-SIG PCIe 3.0 Compliance Workshop
Generic DDR Behavioural Model
Automated ECO Flow for overall cycle time reduction
SoC Interconnect Verification Challenge
Where Have All the IP Vendors Gone? Part 2: Market Maturation
The Honest Process Guy
Enpirion's Value is Not Necessarily in IP
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