SDXC multi card reader IP Controller is compact and proven core with SDR104 mode validated by tier 1 clients on both FPGA and ASIC with UHS-I mode SDXC cards and eMMC/iNAND flash.
SDXC multi card reader IP is fully compliant with the standard SD Host Controller Specifications Version 3.0, SDIO Specifications Version 3.00 and SD physical Layer Specifications Version 3.01.
Ready to ship evaluation platform with bit file available today.
SD/SDIO/eMMC host controller IP uses a 32-bit AHB slave interface to connect to Host system and standard CARD interface on the device side. It uses a parallel interface to load preset values which can be integrated with flash device or EEPROM to define configuration specific to implementation.
This IP also provides support for eMMC 4.41 card interface.
The IP core is portable to either an ASIC or a FPGA. It has been validated on Xilinx Spartan 6 platform.
- Conforms to SD Physical Layer Specifications version 3.01
- support to eMMC4.41 interface
- System Interface – AHB
- Optional Interface – VCI,OCP,AXI, APB
- Supports SDR25, SDR50, SDR104 and DDR50 modes of operation
- Supports up to 104MBps speed
- In-built clock divider
- Assumes external PLL for implementations that choose to use multiplier for greater accuracy of clock frequency
- Configurable FIFO depth
- Supports shared SD bus to connect up to 3 devices
- Supports 1.8V, 3.3V and 3.0V operation. Chip pads are 1.8V. Board level solution is required to support 3.3V and it is controlled by a GPIO pin
- Supports Interrupt
- Supports stop at block gap
- Supports 32-bit AHB slave interface for register configuration and data transfer
- AHB slave interface supports INCR and FIXED address bursts
- Supports DMA channel Req/Ack to integrate with external DMA
- Compact Design
- Portability : ASIC, FPGA
- Validation on Xilinx
- Continuous support during integration, design and verification
- Power and size optimized
- SDR104 mode proven on Xilinx Spartan6
- Very low cost evaluation boards to get started
- Customization support
- Onsite integration support
- Synthesizable Verilog RTL
- Test bench and exhaustive Test cases
- Synthesis constraints and script files
- Sample AHB Slave Driver
- Documentation – User Manual, Verification plan , Validation Report, Synthesis, DFT and integration Guidelines