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New Verification IP
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USB4 v2.0 Verification IP
- Fully compliant with USB4 specification v2.0 (October 2022) and Connection Manager version 2.0.
- Supports USB3.2 Specification, Revision 1.1 and backward compatibility to USB2.0.
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MASS Solution Verification IP
- Support full functionality of APHY as a physical layer
- Support Different PAL for multiple adaption layers for A-pkt conversion
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UCIe Verification IP
- Available in native SystemVerilog (UVM/OVM /VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
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TCP/TCPSW Verification IP
- Available in native System Verilog (UVM/OVM/ VMM) and Verilog
- Unique development methodology to ensure the highest levels of quality
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Simulation VIP for MIPI SoundWire-I3S
- Support testbench language interfaces for SystemVerilog and UVM
- Generates constrained-random bus traffic with predefined error injection
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Ethernet Preemption Verification IP
- Provides Ethernet fully compliant to 802.3-2018 supporting all media independent interfaces for (1/10/25/40/50/100/200/400/800 G)
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MIPI A-PHY Verification IP
- Supports MIPI A-PHY specification 1.0 and 1.1
- Supports single lane and dual lane, point-to-point and serial communication technology
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Simulation VIP for UCIE
- Support testbench language interfaces for SystemVerilog, UVM
- Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
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MIPI I3C Verification IP with IBI feature enabled
- Push-pull mode,
- Open drain switching,
- CCC, command
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UCIe Verification IP
- Support latest PCIe Gen5/6 and CXL 2.0/3.0
- Device and Retimer supported
- Multiple stacks / multiple protocol
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Synthesizable DDR5 Bus Functional Model
- Fully JEDEC spec functionality compliant and reports any non-compliance issues
- Fully cycle accurate model
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SGPIO Verification IP
- Compliant with SFF-8485 Specification for Serial GPIO (SGPIO) Bus revision 0.7.
- Full SGPIO Initiator and SGPIO Target functionality.
Top Verification IP
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USB4 v2.0 Verification IP
- Fully compliant with USB4 specification v2.0 (October 2022) and Connection Manager version 2.0.
- Supports USB3.2 Specification, Revision 1.1 and backward compatibility to USB2.0.
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Simulation VIP for UCIE
- Support testbench language interfaces for SystemVerilog, UVM
- Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
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3
UCIe Verification IP
- Available in native SystemVerilog (UVM/OVM /VMM) and Verilog
- Unique development methodology to ensure highest levels of quality
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4
DDR4 3DS Memory Model
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5
Gigabit Ethernet MAC SystemVerilog OVC Verification IP
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HBM Memory Verification IP
- HBM VIP supports DUT is HMC memory controller and DUT is PHY and supports full set of models including HBM memory module, PHY, and Host memory controller
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USB 2.0 SystemVerilog Verification IP
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HBM Verification IP
- Host and Device agents
- HBM 2.0 specification supported
- Supports legacy mode and pseudo channel mode
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SRAM Verification IP
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HBM Verification IP
- Compliant with the JEDEC JESD235A specification
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11
HBM3 Memory Model
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12
eDP (Embedded DisplayPort) Verification IP
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