D&R News Alert
Innovation in the Semiconductor World
May 25th, 2026

Welcome to the issue of May 25th, 2026 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Arasan MIPI CSI-2 + C/D-PHY IP Solution
Arasan
  • ISO26262 ASIL-C Certified
  • Supporting speeds in excess of 4.5Gbps
  • Supports High-Resolution Camera Sensors. Optimized for Automotive, Mobile & Embedded Vision
  • FPGA & ASIC Ready.
Learn More >>

Foundry and Ecosystem News
■ Samsung Electronics Revises GaN Semiconductor Strategy, Shifts Focus to Foundry
■ Intel Accelerates 1.4nm Foundry Push, Targets Mass Production in 2029
■ United Microelectronics: The Market Is No Longer Pricing It As A Sleepy Mature-Node Foundry
■ AMD Announces Production Ramp of Next-Generation AMD EPYC Processor "Venice" on TSMC 2nm Process Technology
Design and Test Platform
■ PCIe 7.0 Roundup: Test and Timing Tools Emerge as Ecosystem Takes Shape
Artificial Intelligence
■ BrainChip Strikes IP Licensing Deal with ASICLAND
■ Dnotitia Open-Sources AKB on GitHub, an Agent-Native Knowledge Infrastructure for Enterprise AI
■ BrainChip Expands AI Ecosystem with Strategic Software Partners
Data Center
■ Cadence and Microsoft Present New Insights on Data Center CFD Modeling at ITherm
Quantum Computing
■ GlobalFoundries launches Quantum Technology Solutions to scale U.S. quantum manufacturing
■ ST and quantum: bringing industrial scale to a new compute frontier
■ World first: imec presents quantum dot qubit device using High NA EUV lithography
■ U.S. Quantum Bet Puts Hardware First, But Utility Remains the Test
Partner News
■ Weebit Nano raises $15 million via strongly supported SPP
■ Welcoming EMA Design Automation and FlowCAD to Cadence
Business News
■ RESOLVE, a Strategic Initiative Shaping the Future of High-Value-Added Electronic Products in Europe
■ Tata Electronics and ASML Announce Strategic Partnership to Advance the Semiconductor Manufacturing Ecosystem in India
■ Semiconductor-led rebound signals Korea's 13th business cycle expansion
■ Samsung Strike Fallout Spreads to Materials Suppliers; Chip Association Warns of Supply Chain Domino





WAVE63F1: Multi-standard video codec
• supporting AV2 dec, AV1, VVC, and VP9 up to 8K
• Configurable to AV2 decoder only


DDR5 PHY IP for TSMC N4C
• Low latency, small area, low power
• Compatible with JEDEC standard DDR5 SDRAMs up to 8400 Mbps

What they said at
IP SoC Silicon Valley 26

Addressing Physical AI application Challenges with Standards-Based IP
Hezi Saar, Synopsys, Inc.

Legato-Logic: Time-Domain Neural Network Processor IP for Low Power and Low Latency AI Computation
R Scott Hills, VP of Business Development, ANAFLASH Inc.

Advancing AI SoCs through Full digital CIM NPU IP and SRAM Innovation
Hanwool Jeong, CEO, Articron

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