Industry Articles

By Innosilicon

1. Introduction

The Peripheral Component Interconnect Express (PCIe) is a high-speed, serial, point to point computer expansion bus standard developed to supersede legacy interfaces such as PCI, PCI-X, and AGP. Spearheaded by the PCI Special Interest Group (PCI-SIG) consortium, PCIe has evolved through multiple generations, each iteration delivering significant enhancements in bandwidth, scalability, and power efficiency.

Since its initial release in 2003, PCIe has progressed from version 1.0 to PCIe 6.0, with PCIe 7.0 currently in development. A key milestone in this evolution has been the transition from NRZ (Non-Return-to-Zero) signaling to PAM-4 (Pulse Amplitude Modulation with four levels, introduced in Gen6), enabling PCIe 6.0 to achieve data rates of up to 64 GT/s per lane. This effectively doubles the bandwidth of PCIe 5.0 while preserving backward compatibility, a critical requirement for system integrators and silicon designers.

PCIe’s point-to-point architecture eliminates the limitations of traditional parallel bus systems by offering dedicated lanes for each device, resulting in lower latency and higher throughput. It also eliminates contention and improves isolation. Lane configurations ranging from x1 to x16 with x2, x4, x8 as intermediate steps, provide scalable bandwidth tailored to diverse application requirements. Today, PCIe is a foundational interconnect across a broad spectrum of markets, including data centers, AI/ML accelerators, highperformance computing (HPC), automotive systems, embedded platforms, and consumer electronics.

Innosilicon, a leading IP provider, offers a complete PCIe 5.0 solution stack that includes both PHY and controller IPs. Although both layers are crucial to achieving a fully compliant and high-performance PCIe interface, this paper deep dives into the technical challenges of PHY design, highlighting insights drawn from real-world design margins, receiver robustness, and advanced jitter analysis in the context of Gen5 systems.

2. The Evolution of PCIe

Since its introduction in 2003, the PCI Express (PCIe) standard has undergone multiple generations, each delivering substantial improvements in data transfer performance, signaling efficiency, and protocol design. The effective per-lane unidirectional bandwidth has increased dramatically from 250 MB/s in PCIe 1.0 to 7.88 GB/s in PCIe 6.0, with PCIe 7.0 projected to double that to 15.76 GB/s per lane.

PCIe supports multiple lane configurations, enabling scalable bandwidth tailored to specific device requirements and workloads:

• x1 – Single-lane configuration; typically used in for low-bandwidth peripherals such as sound cards and network adapters
• x4 – Commonly used in SSDs, storage controllers
• x8 – Suitable for mid-range GPUs and high-throughput accelerators
• x16 – Standard for high-performance graphics cards and compute accelerators

These configurations allow designers to balance performance, power, and cost across a wide range of applications.

Key Drivers of Bandwidth Growth

Several architectural and technological innovations have contributed to the exponential increase in PCIe bandwidth:

• Higher signaling rates and frequencies with each generation
• Encoding efficiency improvements, such as the transition from 8b/10b (PCIe 1.0/2.0) to 128b/130b (PCIe 3.0–5.0), and the adoption of PAM-4 signaling in PCIe 6.0 and beyond. doubling bits per symbol compared to NRZ
• Enhanced power delivery and signal integrity, enabling reliable high-speed communication
• Advances in silicon process technology, allowing for more complex, power-efficient PHY and controller implementations

These innovations have enabled PCIe to keep pace with the escalating demands of highperformance computing (HPC), AI/ML workloads, cloud infrastructure, and data-intensive applications, while maintaining backward compatibility.

Although the PCIe 6.0 specification was ratified (2022), its adoption across the ecosystem remains limited. This is largely due to the typical generational lag in peripheral support, driven by application-specific requirements, cost constraints, and the time needed for hardware validation and integration. In contrast, the PCIe 5.0 ecosystem has had wider vendor support since ~2021, offering a well-established, high-bandwidth solution that meets the performance demands of high-performance computing (HPC), artificial intelligence (AI), and big data analytics.

Moreover, PCIe 5.0 has gained traction in markets where the full bandwidth of PCIe 6.0 is not yet essential, making it a practical and cost-effective choice for a wide range of applications. As a result, PCIe 5.0 continues to serve as a robust and valuable interconnect standard in both enterprise and emerging technology domains.

Table 1: Evolution of the PCIe Protocol and Data Rates

3. PCIe 5.0 Design Challenges and Solutions

PCIe 5.0 has become a widely adopted interconnect standard, offering high bandwidth and low-latency communication across a variety of lane configurations. Compared to PCIe 4.0, it doubles the data rate to 32 GT/s per lane, delivering up to 63 GB/s of unidirectional bandwidth in a full x16 configuration. This makes PCIe 5.0 well-suited for bandwidthintensive applications such as high-performance computing (HPC), artificial intelligence (AI), advanced storage systems, and networking infrastructure.

One of the key features of PCIe 5.0 is its continued use of the 128b/130b encoding scheme, which offers improved efficiency over earlier generations. However, the leap to higher data rates introduces significant design complexity, particularly in the physical layer (PHY). To maintain performance while minimizing power consumption, designers must implement advanced power management techniques, ensure signal integrity, and address link reliability challenges.

As data rates increase, so do the technical hurdles. Designing a PCIe 5.0 interface, especially the PHY, requires careful consideration of several critical factors. This section focuses on the primary challenges and potential solutions associated with PCIe 5.0 PHY design:

• Signal Integrity (SI)
• Power Integrity (PI)
• High Speed Clock Tree Distribution
• Temperature Drift
• Advanced Process Technology

Signal Integrity (SI) in PCIe 5.0 Systems

As PCIe specifications evolve, data rates continue to rise, reaching 32 GT/s per lane in PCIe 5.0. At these speeds, signal integrity (SI) becomes a critical design consideration, directly impacting system reliability and performance. In a typical PCIe 5.0 Long-Reach (LR) pointto- point link, the signal traverses multiple discontinuities, including:

• Root Complex (RC) package
• Vias
• PCB traces
• Connectors
• Endpoint (EP) device