Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow Chip to Chip (36)
arrow Die-to-die (115)
arrow Intra SoC Connectivity (27)
178 IP
1
150.0
UltraLink Controller
Ultralink controller for high performance die-to-die interconnect on streaming, CXS, and AXI protocols The Cadence Ultralink Controller enables a p...
2
100.0
UCIe PHY & D2D Adapter
Neuron IP’s UCIe PHY & D2D Adapter IP portfolio includes 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S) cores as per the latest UCIe v1.1 specifica...
3
100.0
UCIe-A PHY for Advanced Package (x64) in TSMC (N7, N6, N5, N3)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
4
100.0
UCIe-S PHY for Standard Package (x16) in Samsung (SF5A, SF4X, SF2)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
5
100.0
UCIe-S PHY for Standard Package (x16) in TSMC (N7, N6, N4P, N5, N3)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
6
100.0
Universal Chiplet Interconnect Express (UCIe) Controller
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...
7
75.0
64G UCIe Standard PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
8
70.0
40G UCIe PHY IP on Samsung SF4X
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...
9
60.0
Ncore™ Coherent NoC IP
Built on more than a decade of volume silicon, Ncore™ is silicon-proven coherent NoC IP that is highly configurable, power-efficient, and works with a...
10
60.0
TSMC CLN6FF/7FF Die-to-Die Interface PHY
IGAD2DX01A is a high speed die-to-die interface PHY which transmits data through INFO RDL channels. IGAD2DX01A contains 32 Tx lanes and 32 Rx lanes pe...
11
60.0
Multi-Die interLink (GLink 2.3) IP
GUC multi-die interLink (GLink) IP provides world’s best class solution for high-bandwidth, low-power, low-latency multi-channel interconnection in a ...
12
50.0
40G UCIe PHY for high-density advanced packages
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...
13
50.0
40G UCIe PHY for organic substrate standard packages
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...
14
45.0
XL and 2XL Options for FlexNoC® 5 and FlexGen®
The XL and 2XL Options extend the capabilities of FlexNoC 5 and FlexGen, enabling designers to develop small to large-scale network-on-chip (NoC) topo...
15
45.0
FlexNoC® 5 Interconnect IP
FlexNoC® Interconnect IP by Arteris is used by the world’s top semiconductor design teams as the backbone for on-chip communications in chips that tar...
16
45.0
FlexWay® Interconnect IP
Arteris FlexWay® 5 network-on-chip (NoC) IP is particularly well suited to cost-efficient, low-power IoT edge devices and microcontrollers (MCUs). ...
17
45.0
CodaCache® Last Level Cache IP
CodaCache® addresses modern design challenges through performance-optimized caching, efficient data access, and power optimization techniques. It also...
18
40.0
Non-coherent Network-on-chip (NoC) IP
NC-NoC is a layered, scalable, physically aware configurable NoC supporting multiple clocking schemes for SoCs that do not require coherency. NC-NoC s...
19
30.0
UCIe Die-to-Die Chiplet Controller
Introducing OPENEDGES’ Universal Chiplet Interconnect Express (UCIe) Controller IP, OUC, designed to transform the semiconductor landscape with innova...
20
30.0
High speed NoC (Network On-Chip) Interconnect IP
OPENEDGES is the only total memory system IP company providing both memory controller and on-chip interconnect. OIC is the ORBIT high-speed On-chip In...
21
30.0
Cloud-active NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs
iNoCulator is a cloud-active EDA tool that is used to define the topology of a NoC quickly and easily, configure its parameters and simulate it to mea...
22
30.0
Universal Chiplet Interconnect Express (UCIe) Controller
Integrating multiple chiplets within a single package has become crucial for high-performance computing. CoMira’s UCIe (Universal Chiplet Interconnect...
23
30.0
Coherent Network-on-chip (NoC) IP
C-NoC is a layered, scalable, configurable, and physically aware configurable NoC. It supports mesh, grid and torus topologies with simultaneous exist...
24
29.0
UCIe 2.0 PHY & Controller (Standard & Advanced Package) in 8nm, 5nm, 4nm (8LPU, SF5A, SF4X)
UCIe 2.0 PHY Overview: The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT...
25
29.0
UCIe 3.0 Subsystem for Standard Package (2nm) SF2P (PHY + Adapter + Protocol Mapper)
The UCI Express Specification Revision 3.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, 24GT/s, 32GT/s, 48GT...
26
25.0
32G UCIe Advanced PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
27
20.0
D2D(UCIe 1.0)
The Die-to-Die interface is a functional block that provides a data interface between two chip dies in the same package. MSquare's M2LINK D2D Solution...
28
20.0
D2D(UCIe 1.1)
The Die-to-Die interface is a functional block that provides a data interface between two chip dies within the same package. MSquare's D2D solution, c...
29
20.0
Network on Chip (NoC)
A Network-on-Chip (NoC) is a scalable on-chip communication fabric that connects multiple initiators and targets using packet-based routing. Unlike a ...
30
16.0
Die-2-die interfaces for chiplets - GPIOs for 2.5D and 3D integration
Analog I/O and on-chip Electrostatic Discharge (ESD) protection. Proven on many foundries: TSMC, UMC, GF, TowerSemi, Samsung Foundry, ... Proven in ...
31
15.0
32G UCIe Standard PHY for Samsung
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
32
15.0
32G UCIe Standard PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
33
15.0
Coherent Network-on-Chip (NoC)
SkyeChip's NoC is the first in the world that is able to reconfigure routing paths after tapeout. It is a scalable and area efficient interconnect sol...
34
14.0
40G Ultralink D2D PHY for GF12LP+
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
35
14.0
40G Ultralink D2D PHY for GF12LP+
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
36
14.0
40G Ultralink D2D PHY for Samsung 7LPP
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
37
14.0
40G Ultralink D2D PHY for Samsung 7LPP
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
38
14.0
Universal Chiplet Interconnect Express (UCIe 1.0) Controller
Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols The Cadence UCIe™ Controller i...
39
14.0
Universal Chiplet Interconnect Express (UCIe 1.0) Controller
Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols The Cadence UCIe™ Controller i...
40
12.5
45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
The IKAIKA45GRX is the first generation of UCIe-Class receiver macro on GF 45SPCLO technology node supporting from 1 to 32Gbps with 70mV sensitivity. ...
41
12.5
45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
The IKAIKA45GTX is the first generation of UCIe-Class transmitter macro on GF 45SPCLO technology node supporting from 1 to 32Gbps with 800mVpp single ...
42
11.0
Die-to-Die (D2D) Interconnect
Lightweight die-to-die interconnect solution optimized for highest performance with the lowest power and area overhead...
43
11.0
Die-to-Die (D2D) Interconnect
Lightweight die-to-die interconnect solution optimized for highest performance with the lowest power and area overhead...
44
10.0
MAXVY Universal Chiplet Interconnect Express (UCIe) Verification IP
MAXVY UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of you...
45
10.0
UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)
Unleash the power of the new UCIe based RF Chiplet transceiver. With NEXT Semiconductor's silicon proven 8-bit, 48-Gsps Transceiver, this product ...
46
10.0
UCIe D2D Adapter
The D2D Adapter for UCIe is a scalable adapter layer between one or more protocol components and the UCIe PHY, which ensures efficient data transfer a...
47
10.0
Chip-to-Chip IO Buffer - TSMC CLN4P
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...
48
10.0
Chip-to-Chip IO Buffer - TSMC CLN5
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...
49
10.0
Chip-to-Chip IO Buffer - TSMC CLN5A
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...
50
10.0
Chip-to-Chip IO Buffer - TSMC CLN6FF
Analog Bits’ Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra-short reach environments, using single-end...