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1891 IP
1
100.0
1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
eTopus designs ultra-high speed mixed-signal semiconductor IP solutions for high-performance computing and data center applications. Our 1-56/112Gbps ...
2
100.0
400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
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3
100.0
224G Ethernet PHY in TSMC (N3E, N2P)
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
4
100.0
56G Serdes in 7nm bundled with PCie Gen 5 controller IP
New IP for value conscious designers....
5
100.0
PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 5.0 Base Specification with support of PIPE 5.1 interface spec. Lo...
6
100.0
PCIe 6.0 PHY in Samsung (SF5A, SF4X, SF2)
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...
7
100.0
PCIe 6.0 PHY in TSMC (N6, N5, N4P, N3P, N3E)
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...
8
100.0
PCIe 6.1 Controller
The Rambus PCI Express® (PCIe®) 6.1 Controller is a configurable and scalable design for ASIC implementations. It is backward compatible to the PCIe 5...
9
100.0
PCIe 7.0 Controller
The Rambus PCI Express® (PCIe®) 7.0 Controller is a configurable and scalable design for ASIC implementations. It is backward compatible to the PCIe 6...
10
100.0
PCIe 7.0 Controller with AXI
The Rambus PCI Express® (PCIe®) 7.0 Controller with AXI is a configurable and scalable design for ASIC implementations. It is backward compatible to P...
11
100.0
PCIe 7.0 PHY in TSMC (N5, N3P, N2P)
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...
12
100.0
PCIe 7.0 PHY IP supporting the latest features of the evolving PCIe 7.0 specification to enable 128 GT/s and up to x16 lane configurations
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...
13
100.0
PCIe 7.0 Retimer Controller
The Rambus PCI Express® (PCIe®) 7.0 Retimer Controller provides a complete digital data path solution that delivers best-in-class latency, power and a...
14
100.0
PCIe 7.0 Switch
The Rambus PCI Express® (PCIe®) 7.0 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC and FPGA implementations. It enable...
15
100.0
PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
Multiprotocol low latency, low power SERDES IP....
16
100.0
UCIe-A PHY for Advanced Package (x64) in TSMC (N7, N6, N5, N3)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
17
100.0
UCIe-S PHY for Standard Package (x16) in Samsung (SF5A, SF4X, SF2)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
18
100.0
UCIe-S PHY for Standard Package (x16) in TSMC (N7, N6, N4P, N5, N3)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
19
100.0
UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
Blue Cheetah is a leader in Die-to-Die (D2D) interconnect solutions for chiplets in very advanced and low-cost packaging applications. BlueLynx™ is a...
20
100.0
VDC-M (VESA Display Compression-M) Decoder
The Rambus VESA VDC-M 1.2 Decoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliv...
21
100.0
VDC-M (VESA Display Compression-M) Encoder
The Rambus VESA VDC-M 1.2 Encoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 encoder to deliv...
22
100.0
VESA DisplayPort 1.4 Forward Error Correction (FEC) Receiver
The DisplayPort Forward Error Correction (FEC) Receiver IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPo...
23
100.0
VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA Displa...
24
100.0
VESA DSC (Display Stream Compression) 1.2b Video Decoder
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25
100.0
VESA DSC (Display Stream Compression) 1.2b Video Encoder
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26
100.0
VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs
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27
100.0
VESA DSC 1.2b Encoder for Xilinx FPGAs
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28
100.0
MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
The MXL-CDPHY-6p0G-CSI-2-RX+-T-N6 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificat...
29
100.0
MIPI C-PHY/D-PHY Combo RX+ IP (4.5Gsps/4.5Gbps) in TSMC N5
The MXL-CD-PHY-CSI-RX+-T-N05 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...
30
100.0
MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
Arasan's MIPI C-PHY is designed and compliant with latest MIPI C-Phy Standards. The MIPI C-PHY V1.2 improves throughput over a bandwidth-limited ch...
31
100.0
MIPI CSI-2 Controller Core V2
The Rambus CSI-2 Controller Core V2 is the second generation CSI-2 controller core. It is further optimized for high performance, low power and small ...
32
100.0
MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
The Arasan MIPI CSI-2 Receiver IP Core functions as a MIPI Camera Serial Interface Receiver, between a peripheral device (Camera module) and a host pr...
33
100.0
MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
Combination MIPI CPHY-DPHY Analog Interface The MIPI C-PHY V1.2 improves throughput over a bandwidth limited channel, allowing more data without in...
34
100.0
MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
Arasan delivers you MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete G...
35
100.0
MIPI D-PHY Universal IP in TSMC 22ULP
The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2....
36
100.0
MIPI DSI Receiver Controller v1.3
The Arasan DSI Device Controller IP is designed to provide MIPI compliant high speed serial connectivity for mobile display modules with Type 1 to 4 a...
37
100.0
MIPI DSI Transmit Controller v1.3
The Arasan DSI Transmit Controller IP is designed to provide MIPI DSI 1.3 compliant high speed serial connectivity for mobile host processors using 1 ...
38
100.0
MIPI DSI-2 Controller Core
The Rambus DSI-2 Controller Core is the second generation DSI controller core. It is further optimized for high performance, low power and small size....
39
100.0
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devices, including graphic...
40
100.0
Globalfoundries 12nm MIPI D-PHY V1.2@2.5GHz
Arasan Chip Systems announces the immediate availability of its MIPI D-PHY(SM) Globalfoundries 12nm FinFET process nodes. Arasan's D-PHY Global Foun...
41
100.0
Universal Chiplet Interconnect Express (UCIe) Controller
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...
42
100.0
Complete USB Type-C Power Delivery PHY, RTL, and Software
The OTI9108 is a complete single transceiver front end for data USB PD Type-C (baseband) communications. It has a register interface which, with an MP...
43
100.0
Compute Express Link (CXL) 3.1 Controller
The Rambus Compute Express Link® (CXL®) 3.1 controller is a parameterizable design for ASIC and FPGA implementations. It leverages the Rambus PCIe® 6....
44
100.0
Low-Latency SerDes PMA - 10GbE, 25GbE
Best(lowest)-in-class latency 10GbE/25GbE SerDes PMA....
45
100.0
USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...
46
100.0
USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...
47
100.0
USB4 Controller & Router IP
The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router,...
48
100.0
USB4 PHY in Samsung (SF4X)
The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router,...
49
100.0
USB4 PHY in TSMC (N7, N6, N5, N4P, N3E, N3P)
The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router,...
50
100.0
ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
The VESA DSC 1.1 Encoder IP Core for automotive displays implements a fully compliant VESA DSC 1.1 encoder. It contains additional safety features to ...