The world of System-on-Chips (SoCs) is evolving - with the advancement of generative AI, the increasing demand for high-performance compute, and the innovative shift towards multi-chiplet architectures, system complexity is advancing at an increased pace. And with complexity comes an even greater challenge: debugging complexity.
Silent data corruption, elusive timing-sensitive bugs, and intricate interactions across heterogeneous components are becoming increasingly difficult to root cause. Without the right kind of deep, system-wide visibility, engineers can find themselves in a frustrating cycle of trying to diagnose problems that seem to vanish and reappear, consuming valuable time.
In this blog, we introduce Tessent UltraSight and how it can help with debugging complexity.
It's not just about the Processor Core anymore, it’s also about the system
Functional monitoring offers the essential capability to non-intrusively observe and collect data, ensuring that the entire system behaves as expected thus accelerating debug efforts. This involves crucial activities like gathering bus transaction activity and statistics across your System-on-Chip (SoC) to pinpoint bottlenecks or unexpected behavior, or analyzing the behavior of critical hardware signals well beyond the immediate vicinity of a processor.
These insights provide the crucial context needed to root-cause issues that extend beyond the instructions executed by the processor core, offering a holistic view of your system's operation.
Debugging complex SoCs with Tessent UltraSight
Modern SoCs are incredibly complex, getting real-time and deep visibility into their functional behavior can be a huge challenge. That's where Tessent UltraSight comes in - Tessent UltraSight offers a complete functional monitoring and debugging solution, designed to streamline and accelerate engineering efforts throughout the entire SoC development lifecycle.
- Embedded functional monitoring hardware IPs:
- A suite of highly configurable, pre-verified, and silicon-proven hardware IPs that serve as your system's built-in intelligence. These are the “eyes and ears” embedded directly into your design.
- EA Builder for design engineers: Simplify generating UltraSight hardware subsystems with user-friendly interface
- This new tool helps reduce integration time for design engineers by generating functional monitoring and debug subsystem blocks. Within the tool, design engineers can specify which functional monitors they want and manage the parameters and interfaces. The tool automatically adds the communication infrastructure.
- It automates the creation of necessary testbenches for the generated subsystem.
- It provides industry-standard IP-XACT for clear and consistent register descriptions, streamlining integration.
- Seamless UVM integration with UltraSight verification IP
- To ensure smooth integration into your existing verification flows and significantly accelerate verification efforts, UltraSight provides a robust, IEEE 1800.2 compliant, UVM-based Verification IP. This VIP serves as a comprehensive test environment, complete with sequence libraries and example integration tests, enabling verification engineers to carry out thorough system-level verification of the Embedded Analytics IP deployed within an SoC.
- Host Suite software for UltraSight configuration, data capture, and real-time insights
- For real-time control and data access, Host Suite offers a collection of powerful C++ and Python APIs, and processor run control applications that interface with GDB and OpenOCD. These allow software engineers to configure functional monitoring at run-time and obtain critical monitoring data during software execution.
Efficient monitoring and industry-standard compatibility
Gathering functional monitoring data from can quickly become an overwhelming stream, the sheer volume of data can overwhelm the infrastructure to be transferred off-chip, let alone burdening the system bandwidth and adding complexity in post-processing.
To address this, Tessent UltraSight provides the following intelligent features:
- Advanced filtering and cross-triggering: Instead of capturing everything, UltraSight allows you to decide what data to collect and when. You can capture only what's needed around a specific event, significantly mitigating high bandwidth issues. This smart approach means you focus on relevant data, not noise.
- Statistical gathering: Beyond raw traces, UltraSight can collect valuable statistics on functional behavior, offering high-level insights without the massive data footprint.
- Industry-standard interfaces: UltraSight ensures compatibility with common transport mechanisms like JTAG (IEEE 1149.1), cJTAG (IEEE 1149.7), USB, and AMBA AXI, fitting effortlessly into your existing debug environment.
Summary
Tessent UltraSight isn't just a collection of hardware monitors, it's a comprehensive solution that combines embedded hardware IP with powerful host software to provide deep visibility into complex SoCs, supporting the development and optimization of high-performance embedded software.
Key advantages of Tessent UltraSight include:
- Comprehensive system-wide functional monitoring: Gain deep insights across your entire SoC
- End-to-end solution: A complete package consisting of embedded IP and host software for a seamless experience.
- Efficient debugging capabilities: Smart filtering, statistical gathering, and cross-triggering mitigate bandwidth issues and help you focus on critical events.
- Industry-standard integration: Compatible with common interfaces and tools, ensuring easy adoption into your existing workflows.
Siemens' deep expertise and leadership in RISC-V debug and trace solutions are reflected in Tessent UltraSight's capabilities.
For more information on Tessent UltraSight and other advanced embedded analytical solutions from Siemens EDA, please visit www.siemens.com/Tessent-Embedded-Analytics