The NoC-Centric, CHI-Native Path Forward
SignatureIP Engineering Team
Center of Excellence for Compute and I/O Subsystem IP
Abstract. The shared-bus and crossbar interconnects that defined SoC architecture for two decades have run out of room. Workloads have changed faster than the buses meant to serve them. Processor counts have grown, coherency requirements have spread beyond CPU clusters into accelerators, and integration density has pushed past what arbitrated buses or large crossbars can support without prohibitive area, power, and timing penalties. Network-on-Chip fabrics are now the default on-die transport for AI accelerator, server-class, and high-end automotive SoCs. Four forces drive the migration: heterogeneous-coherency AI workloads, automotive ISO 26262 safety requirements, chiplet disaggregation through UCIe 2.0, and advanced-node wire-delay constraints. This paper examines each force, explains why packet-switched NoC fabrics with directory-based coherency address them, and presents the SignatureIP portfolio built for this transition.
Index Terms. Network-on-Chip; AMBA CHI Issue E.b; AXI4; SoC Interconnect; Cache Coherency; Directory-Based Snoop; ISO 26262; Automotive ADAS; Chiplet Disaggregation; UCIe 2.0; Inoculator RTL Generation