Every core has its own cache. That's the performance win. It's also the consistency problem. This paper covers how hardware coherency solves it — and what it costs when you get it wrong.
Modern SoCs have grown past the point where broadcast snooping is a viable coherency strategy. A fabric that worked at four coherent agents starts to buckle at twelve, and coherency traffic alone can absorb nearly 30 percentage points of available memory bandwidth under load. This paper traces the architecture from the basics of why caches create inconsistency, through the MESI state machine and its limits, to AMBA CHI Rev E.b and the direct-transfer mechanisms that define production-grade coherency at SoC scale. It covers the real measured cost of coherency traffic, the design choices that separate I/O coherency from full coherency in heterogeneous SoCs, the new constraints that chiplet boundaries impose, and what ISO 26262 functional safety actually requires of the coherent data path. Throughout, it shows how SignatureIP's C-NOC, NC-NOC, Proxy Cache, and Inoculator address each problem in the stack.