Industry Articles

Caliptra, an open-source silicon root of trust (RoT) project governed by the Open Compute Project (OCP), defines comprehensive digital logic and firmware specifications. However, with the introduction of Caliptra 2.1, which incorporates the OpenTitan-referenced one-time programmable, OTP, controller interface and unique device secret, UDS, obfuscation mechanisms, SoC designers face a significantly higher threshold for physical layer integration. This article analyzes the implementation requirements for UDS generation, entropy source quality, and secure storage within the Caliptra ecosystem. It further explores how integrating physical unclonable function-based root of trust, PUFrt, a solution supporting the OpenTitan Interface (OTI), serves as a robust hardware security anchor to construct a complete security system compliant with zero trust architectures.

Limitations of Digital Root of Trust Standards at the Physical Layer

While Caliptra provides standardized RTL, it presupposes that the underlying hardware can deliver ideal physical primitives. In reality, SoC designers attempting to independently integrate these functions often encounter four major technical challenges:

1. Physical visibility risks of eFuse: traditional eFuses rely on electromigration, current-induced fusing, for programming. Under scanning electron microscopy (SEM) or optical inspection, the physical state of the fuse is clearly discernible. If a UDS or obfuscation key is stored directly in standard eFuses, attackers can employ reverse engineering techniques such as delayering to extract the plaintext key, causing the chain of trust to collapse at the physical layer.

2. Compliance barriers for True Random Number Generators (TRNG): Caliptra requires entropy sources to pass rigorous health checks and comply with NIST SP 800-90B standards. However, developing digital entropy sources in-house often encounters entropy instability, which not only incurs area and power overhead but also makes it difficult to achieve NIST ESV (entropy source validation) certification.
3. Global break risks with metal keys: although Caliptra specifications support using a metal key as an obfuscation key, the lack of per-die uniqueness poses a severe risk. If a single chip is reverse-engineered, the obfuscation mechanism for the entire product line is rendered useless, creating a "global break" security vulnerability.

4. Challenges in disaggregated integration and verification: sourcing OTP, TRNG, and PUF IPs separately necessitates managing multiple interface protocols and timing requirements. Specifically, with Caliptra 2.1 recommending the OTI and hardware zeroization mechanisms, inconsistent support across different IPs forces design teams to expend significant resources on integration and design verification, drastically increasing development costs and time-to-market.

Graphical presentation of the Caliptra Subsystem with PUFrt as the hardware security anchor

PUFrt as a Hardware Security Anchor for Caliptra 2.1

PUFrt serves as a turnkey, integrated solution for secure storage and entropy generation. Its architectural design aligns directly with Caliptra 2.1 specifications, offering out-of-the-box compliance, particularly regarding OTI support and UDS obfuscation mechanisms.

1. Protecting UDS and Key Management to Eliminate Risks with Global Key

Addressing the obfuscated UDS requirements of Caliptra 2.1, PUFrt provides a secure and flexible implementation path:

• Optional zero-touch UDS provisioning: PUFrt also provides the capability to utilize the NeoPUF physical fingerprint directly as the UDS. This enables projects adopting this approach to bypass the cumbersome traditional key injection process and associated hardware security module infrastructure, significantly reducing manufacturing costs.
• Mitigating metal key risks: utilizing the PUF as the chip-native UDS eliminates risks associated with eFuse attacks. Even if the global RTL metal key is compromised, the security of the UDS remains intact, as it is derived from a unique physical source rather than a shared secret.
• Enhancing OTP privacy: PUFrt’s built-in NeoFuse is encrypted using the NeoPUF on-chip fingerprint. Even if secure data is stored in the OTP, it only exists in ciphertext. Furthermore, NeoFuse possesses anti-optical inspection characteristics, effectively addressing the vulnerability of traditional eFuses to SEM readout.

2. Entropy Source: The Direct Path to NIST Compliance

The built-in physical entropy source and TRNG within PUFrt are specifically engineered to meet Caliptra’s high standards:

• Built-in physical entropy: PUFrt includes a native physical noise source capable of outputting high-quality raw entropy, satisfying Caliptra’s min-entropy requirements without complex post-processing.
• Pre-verified and silicon-proven: the entropy source architecture has already achieved NIST ESV certification and is silicon-proven. SoC designers don’t need to worry about TRNG quality failures during the final product certification phase, avoiding the costly risk of a mask respin.

3. Aligned Integration: Interface Compliance, Entropy, and Zeroization

PUFrt is not merely a stack of IPs; it is fully adapted for the Caliptra subsystem. Customers have already successfully completed system integration, passed relevant verifications, and entered mass production phase:

• Native OTI support: features a built-in OTI that connects directly to Caliptra’s fuse controller without requiring additional wrapper logic, ensuring the precise implementation of secure OTP storage functions.
• Physical entropy source: provides NeoPUF static entropy as the obfuscation key and delivers native dynamic entropy to Caliptra to drive its TRNG core operations.
• Critical register zeroization: supports a temporary zeroization security function for critical registers, allowing for the immediate clearing of sensitive data during runtime to strengthen execution-state security.
• IEEE 2883 compliant hardware zeroization: addressing device retirement or reset requirements, PUFrt supports a hardware-triggered purge-level clear signal. Once triggered, it instantaneously executes cryptographic erase, permanently destroying all internal sensitive registers and keys. This not only ensures the irreversibility and thoroughness of data destruction but also meets Caliptra 2.1 requirements for attested secure erase – a system-level capability that is difficult to achieve when assembling disparate IPs.

4. Architectural and Lifecycle Advantages

For SoC architects, selecting PUFrt is not merely about choosing an IP; it is about opting for a highly efficient and optimized deployment path for Caliptra:

• Maximizing development resource efficiency: eliminates the engineering complexity associated with integrating discrete eFuse, TRNG, and PUF Ips within a single SoC. With native OTI support, it drastically simplifies interface adaptation and significantly shortens the design verification cycle, allowing R&D teams to focus on core feature development.
• Strengthening physical security and reliability: fundamentally resolves issues associated with eFuse visibility and shared metal keys at the architectural level. This elevates the security design of the overall hardware trust anchor to a protection level aligned with Evaluation Assurance Levels above 5 for Common Criteria (CC EAL 5+), ensuring the long-term robustness and reliability of the product.
• Accelerating compliance and time-to-market: by leveraging pre-hardened and pre-verified TRNG and physical implementations, PUFrt expedites the process for end products to achieve OCP and FIPS-related security certifications, significantly shortening time-to-market to seize early market opportunities.

Conclusion

While Caliptra establishes the logical standard for the Silicon Root of Trust, we propose PUFrt as a hardware root of trust that fills the critical missing pieces in physical implementation. By combining the naturally derived fingerprints from quantum-tunneling-based NeoPUF with NIST ESV-compliant dynamic entropy, developers can construct data center chips that meet Open Compute Project specifications while achieving strong resilience against physical attacks, without sacrificing performance or area. This approach delivers end-to-end compliance from logic to physics and accelerates market entry by significantly reducing development efforts, particularly when paired with platform-level integration planning and validation.