A SignatureIP technical white paper on partitioning on-die transport for modern multi-core SoCs
SignatureIP Engineering Team
Center of Excellence for Compute and I/O Subsystem IP
Abstract
The on-die transport choice in a modern SoC is no longer a single decision. It is a partitioning problem: which traffic needs hardware-enforced cache coherency, and which does not. Coherent fabrics built around AMBA CHI Rev E.b (Issue E) with a directory-based home node carry the traffic between CPU clusters, GPU compute, and AI/ML accelerators that must see the same view of shared memory. Non-coherent fabrics built around AXI4 (and AXI3, AXI4-Lite, AXI4-Stream, AHB, APB) carry I/O, peripheral, and legacy traffic that has no need for coherency. Picking a single fabric for everything wastes silicon, bandwidth, and power on traffic that does not need coherency, or forces software cache maintenance that does not scale on traffic that does. The pattern that current production SoCs converge on is a coherent fabric, a non-coherent fabric, a bridging cache between the two for I/O coherency, and bidirectional protocol bridges for migration and interop. SignatureIP delivers this as one integrated system: C-NOC as the CHI coherent fabric, NC-NOC as the non-coherent fabric, Proxy Cache as the bridging cache, AXI2CHI and CHI2AXI as the protocol bridges, ATC as the IOMMU-style translation cache, PCIe Controller and CXL Controller (with the pre-integrated CXL Subsystem) as the standardized off-die attach paths, AXI4-LLL as the link-layer IP for photonic and copper serial interconnect, Ethernet IP as a representative non-coherent master, and Inoculator as the cloud-based topology generator. Functional-safety support across the portfolio is on the SignatureIP roadmap.
Index Terms, AMBA CHI, AXI4, network-on-chip, directory-based snoop filter, I/O coherency, proxy cache, IOMMU, PCIe 6.x, CXL 3.x, Flex Bus, UCIe, mixed-fabric SoC, heterogeneous SoC.