Industry Articles
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Flexible Embedded Processors for Developing Multi-Standard OFDM Broadcast Receivers
(Friday, October 15, 2004)
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Selecting PLLs for ASIC Applications Requires Tradeoffs
(Tuesday, October 12, 2004)
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OCP-based Memory Controller IP Offers Optimal Power and Performance Requirements for 3G Applications
(Tuesday, October 12, 2004)
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Configurable Processors for Video Processing SOCs
(Monday, October 11, 2004)
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The Importance of Thorough Signal Integrity Analysis - A Signal Integrity Case Study
(Monday, October 11, 2004)
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Processor Architecture for High Performance Video Decode
(Monday, October 11, 2004)
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An Innovative RF CMOS IP Using a 10 GHz VCO for Direct Conversion WLAN
(Monday, October 11, 2004)
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Licensable Processors - More than just design IP
(Monday, October 11, 2004)
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Standards-Based IP Cores Ease Networking IC Design
(Monday, October 11, 2004)
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IP Cores for accelerating JPEG2000
(Monday, October 11, 2004)
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Under the Hood of Library IP (by Brani Buric and Mike Colwell, Virage Logic)
(Monday, October 11, 2004)
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Synopsys DesignWare Verification IP and Vera Accelerate Complex SoC Validation
(Monday, October 11, 2004)
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PLLs Plot An Adjustable Course
(Monday, October 11, 2004)
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Mentor Graphics Executive Viewpoint : Increasing System Complexity Drives Need for IP
(Monday, October 11, 2004)
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Virage pulls back the covers to detail platforms
(Monday, October 11, 2004)
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How Tensilica verifies processor cores
(Monday, October 11, 2004)
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Designing 5-Gbit/s Serdes: Steering Through a Road Filled with Potholes
(Monday, October 11, 2004)
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IP Cores for FPGAs
(Friday, October 8, 2004)
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In-Depth: Making platform ASICs easier to use
(Friday, October 1, 2004)
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Realising the Full Potential of Multi-core Designs
(Friday, October 1, 2004)
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Designing USB into embedded systems
(Friday, October 1, 2004)
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Understanding the reuse of a DSP architecture for different designs (Ceva)
(Tuesday, September 21, 2004)
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FPGA design from the outside in
(Friday, September 17, 2004)
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Making SPI-4.2 Implementations More Efficient: Part 2
(Friday, September 17, 2004)
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New Wave of FPGA Prototyping for System-on-Chip Designs
(Friday, September 10, 2004)
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Tunneling SPI-4.2 Through an Advanced Switching Fabric
(Friday, September 10, 2004)
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Multi-Ports Eliminate Baseband Processing Bottlenecks
(Friday, September 3, 2004)
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Reconfigurable illogic
(Friday, August 27, 2004)
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IEEE 802.11i and wireless security
(Friday, August 27, 2004)
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Solving AMR Speech Codec Porting Challenges
(Friday, August 20, 2004)
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Collaboration Makes New Commercial Ultra Low-Power Solution Accessible To Designers
(Tuesday, August 17, 2004)
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Making Converter Integration Happen in Mobile Phone SoCs
(Tuesday, August 10, 2004)
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System-in-package becomes SoC alternative
(Tuesday, August 10, 2004)
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Today's DSP Design Challenge - Power Efficiency
(Friday, August 6, 2004)
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Managing Memory Usage in VPLS-Enabled NPU Designs
(Friday, July 23, 2004)
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How to calculate CPU utilization
(Tuesday, July 20, 2004)
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Scalable IP Core of Vector Stream Cipher
(Wednesday, July 14, 2004)
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Making the UWB PHY a "Transparent Patient"
(Friday, July 9, 2004)
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Power Reduction Techniques for Ultra-Low-Power Solutions
(Tuesday, July 6, 2004)
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Sigma-delta techniques extend DAC resolution
(Friday, July 2, 2004)
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Scatternet - Part 1: Baseband vs. Host Stack Implementation
(Friday, July 2, 2004)
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Simplifying SoC design with the Customizable Control Processor
(Friday, June 25, 2004)
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Achieving Better Code Optimization in DSP Designs
(Friday, June 25, 2004)
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Configurable Processors: Ready for Prime Time
(Tuesday, June 22, 2004)
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A Low-Power 16-channel AD Converter and Digital Processor ASIC
(Friday, June 18, 2004)
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Meeting the Challenges of VoIP ATA Designs
(Tuesday, June 15, 2004)
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System-Level Design Tackles Tough Soft Radio Framework Challenges
(Tuesday, June 8, 2004)
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IP Core of Statistical Test Suite of FIPS 140-2
(Friday, May 28, 2004)
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Evaluating Data Management Software
(Tuesday, May 25, 2004)
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Verification = IP = Verification = IP =... - Part 2 (By Dr. Aart de Geus)
(Friday, May 14, 2004)
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