by Phil Casini Vice President MarketingSonics, Inc.
SoC design has become very complex because the convergence of multimedia and data communications onto a single device complicates SoC architecture significantly. The chip internal interconnect design must support heterogeneous multiprocessing topologies (via cross bars and shared links) so that the data flows are optimized on and off chip through the hierarchy of connectivity required. This translates into a heightened need to consider pre-designed and pre-verified internal interconnects capable of meeting the new challenges as a solution alternative to developing equivalent interconnects in-house.
This paper discusses the economic benefits realized when outsourcing complex SoC interconnect design and using third party products, such as Sonics SMART Interconnects. The paper first uses a volume distribution for a given mobile handheld market segment as an example to show how small time to market advantages can have a dramatic impact on realized gross profits. Secondly the paper uses an output production economic model to quantify the underlying productivity gains realized by outsourcing the internal interconnect design which enables time to market improvements. Finally the paper discusses the benefits of adopting an outsourced interconnect strategy as a basis for a platform-architecture that enables a family of products to realize compounding benefits.
Introduction: Its 2005….. Time for an Interconnect Strategy Change
Just a few short years ago, SoC design was relatively straight forward. Consider the original DVD player, essentially a decoding system. The major decision point was the choice of embedded processor. Logic added was complimentary and easily verifiable.
Today is a much different world. The convergence of latency dependent data communications and high throughput digital multimedia streaming has caused a shift in SoC design architecture from single to multiprocessing, subsystem style designs. Today, DVD players have morphed into DVRs, which can include high definition processing and program recording features among others. These new features exponentially increase the complexity of data flows and as a result, has shifted SoC architecture from a data processing centric perspective to a data flow centric perspective. What does this mean?
The major SoC design problem is no longer the methods by which data will be processed, but the method by which data will flow through the many connections on the device to meet all the requirements. Given the necessity for multiple heterogeneous processors, the the complexity of increasing protocol speeds, and as always, external memory bandwidth, data flow architecture is now very complex.
This complexity reaches far beyond what standard processor style buses can provide, because the heterogeneous style of multiprocessing that has emerged for SoC architectures requires extreme flexibility between processor or subsystem interfaces in order to achieve high utilization of the processing elements and minimize data flow bottlenecks. Microprocessor style busses were never designed for this purpose and typically it is left up to the SoC architecture to engineer a super set solution. With complexities escalating rapidly, the economics no longer makes sense to undertake the engineering effort required to keep pace.
SoC solutions now require complex protocol management of its own, extremely well planned modularity between the interconnect and its data processing points, and even network functions such as Quality of Service (QOS), Security, and Power Management to ensure end requirements are met.
It follows then that as it did when embedded processor design eventually became complex and the economics shifted to outsourcing and acquiring pre-designed solutions, so too is the time that the complexity of internal interconnects has shifted the economics to outsourcing and purchasing third party solutions.
The shift is the catalyst for a new market segment for intelligent internal interconnects (I3) which is rapidly forming to service the needs of SoC developers. This new segment differs greatly from embedded processor, memory, or even logic segments because it deals strictly with data flow, not data processing. As such, the emerging solutions from this segment serve a broader application space; enabling true platform architectures to emerge with economies of scale not realized in traditional IP style market segments.
Section 1: Quantifying the impact of outsourcing Interconnects
This paper focuses on a segment of the mobile handset market to highlight the economic shift. However, the economics apply to many high volume markets that are highly competitive. The following chart represents the segmentation of the mobile handset market according to iSuppli Corporation:
The paper has selected the fast growing high end smart phone segment and assumes a new model will be built for 2005 that streams multimedia, supports PDA functions, and has classical data communications capability (telephony and email for example).
Assuming that the market segment will follow a normal distribution of its 52 million units over a 32 month period, The Total Available Market (TAM) for the segment is represented by the following:
The complexity of such a smart phone, given that both conventional data communications and advanced streaming multimedia must both be supported to meet end requirements, assures that a multiprocessor approach must be taken which raises the difficulty of the SoC design to a high degree of complexity. Utilization rates achieved for the processing elements contained in the SoC will have a significant effect on the performance, power consumption, and area of the SoC, and its competitiveness in the market as a result.
Assuming that much of the software is mature for the segment, the dominant architecture task to develop such a complex SoC will be the data flows. The performance of the internal interconnect will therefore have a high impact on the competitiveness of the SoC product because of its high bearing on the utilization rates achieved for the processing elements. Variable data widths, complex arbitration schemes that can guarantee low latency to some processors and high bandwidth to others, security, error, and even power management, all effect the utilization of the processing elements on the chip, and must now be present to meet end user requirements. This creates the need for a layer of “intelligent” services that must be designed, in addition to the common bus style elements, in order to manage heterogeneous multiprocessing architectures.
As such, the paper will assume that the intelligent internal interconnect is the most important design decision that will drive the SoC architecture for this example, and will isolate the intelligent internal interconnect solution as the one risk item (for the purpose of showing the economic shift) that can most effect the development cycle and success of the product in the segment.
The research performed by Sonics modeled four companies that would compete in the segment (Companies A through D). For the sake of brevity, only the results of the top two companies are presented. Suppose then that Company A enters into the market with the first version of the product, and Company B enters the market 3 months later. What are the gross profits for Company A and Company B? Since this segment is highly elastic, that is very sensitive to time and price competition, overlaying an aggressive gross profit erosion curve over the distribution curve shows the true market dynamics:
Assuming that the market segment Average Selling Price (ASP) for the SoC starts at $18 ($11.30 cost @ 66% GPM) and drops to $13.50 ($10 cost @35% GPM) at month 32, Company A and Company B gross profits can then be estimated using the graphs above. The table below shows the results of the spreadsheet calculations which highlight the impact on gross profit as a result of a 3 month “delay” in market entry by Company B.
The results show that Company A enjoyed a 25% increase in revenue and a 30% increase in gross profits over the life of the volume distribution when compared to Company B.
If the technical merits of both company’s products are “normalized”, that is both companies started their development cycles at the same time, using the same microprocessors, software stacks, engineering talent, etc., what accounted for the difference in time to market? Three months represents the difference in one spin on the design given the level of SoC complexity. Since the internal interconnect is the primary area of SoC design risk, one iteration of a complex internal interconnect design and verification process can conservatively account for the 3 months.
If we assume then that Company A utilized a intelligent internal interconnect from a third party, one that provides the necessary services in addition to bus features to meet end requirements, and took advantage of automated tools that accurately predict the intelligent internal interconnect’s behavior before and during the early phases of the physical chip design, the decision to outsource the intelligent internal interconnect lowered Company A’s risk, “saving” 1 design spin when compared to Company B, which resulted in Company A capturing the premium designs in the market that yielded the $25M of additional gross profit.
Company B, utilizing an in house design team, realized a similar interconnect solution but because it had to engineer the intelligent services in addition to the bus features, the resulting solution did not have the maturity and robust testing that the third party interconnect had, and did not have the same level of tools automation provided by the third party internal interconnect supplier. Company B’s approach lead to 1 extra design spin and lost out on $25M gross profit.
It is somewhat irrelevant that an in-house design team can design a similar interconnect solution as one that can be acquired from a third party. What is important was that Company A reduced a major risk item in the SoC development process by deciding to outsource the internal interconnect and boosted its revenue and profitability significantly as a result.
It is also worth mentioning that a second order advantage of outsourcing the interconnect is the accommodation of market requirement changes late in the design cycle. Since Company A chose an I3 product, making changes to any of the cores, or the interconnect itself, are virtually independent events that can be isolated to minimize re-engineering, a benefit of modularity and the loosely coupled methodology. These changes then are only incremental to the overall development process and top level verification is still reached in a much faster time.
In conclusion then, 1 spin in highly elastic markets can have a huge impact on success.
Section 2: Why outsourcing Interconnect improves productivity
Why does outsourcing the interconnect result in faster time to market? The answer lies in looking at the impact of introducing new interconnect technology innovation, in light of a capital and labor mix for a company that defines the pace of its output production versus expending labor to create a similar solution.
In the following example the output productivity levels were held constant and capital and labor mixes varied to show how the outsourcing decision of Company A enables them to realize a time to market advantage over Company B.
Consider the following output curve of the SoC development team for Company A. The “before” curve represents the estimated capital and labor costs for Company A to develop their share of the 52M SoCs over a 32 month period, based on its tools chain (capital) and its team size and expertise (labor). The net effect of purchasing an intelligent internal interconnect solution is a technology input that makes the tool chain and labor more efficient. As such it serves to permanently shift the entire productivity of Company A’s SoC development team to the “after” curve. Company A can now produce the same amount of output more efficiently.
This has significant ramifications for Company A, because using a platform strategy, Company A can now deliver more products with the same labor force faster than before. Section 3 will quantify the compound benefits of this shift.
Now consider Company’s B decision to invest in developing and sustaining the internal interconnect. This decision has a different impact on output because there is a labor burden to engineering an equivalent solution in lieu of a technology input. Therefore Company B’s “make” decision serves only to move their output point from point A to point B on the same output curve, but does not shift the curve.
The added labor investment made by Company B is not justified, because Company A’s “buy” decision actually impacted a greater change in output productivity. Assuming Company A and B started with the same output curve, Company A has a sustainable advantage.
The findings from these charts are consistent with market research conducted that measures the costs of IP as a function of overall silicon costs. Below is a chart produced by Semico Research that measures the relative impact of IP on silicon cost and substantiates the findings of this paper:
Given that “buy” in principle is a better decision over “make” then, the next question is to quantify the cost of adopting the two approaches to ensure purchasing the interconnect does not outweigh its benefit when compared to the higher labor burden approach of an in house design. The table below represents Sonics’ estimates of the comparative costs of the two approaches:
The table then shows that the total costs are relatively the same, preserving the economic benefit realized by Company A.
Section 3: The Compound Benefits of an Outsourced Interconnect Strategy
Up until now, this paper has focused on a single product design. In this section the results of a platform strategy are quantified over a family of products in order to show that the benefits of an outsourced interconnect compound over time.
Looking back at Company A, their decision to outsource enabled them to secure more volume over the lifetime of the product. That has three advantages. First is more profits which can be invested to improve its business even further. Second, increased market share relative to its competitors, and third increased engineering output with lower design risk which enables them to start and complete more projects even faster.
Company A will gain even more volume, more profit, more market share, and also start new projects even earlier as time passes. Company A realizes compounding profits then that can be shown below (over 6 designs over 133 months in this example):
With compounding profits quantified, it is easy to see increasing ROI for Company A even though Company A continues to increase its investment in purchasing interconnects over time. In the above analysis, Company A achieves $150M more in profit over the 6 designs when compared to Company B.
While this paper focused on Company A and B, the research conducted for this paper was conducted over four companies each entering the market in 3 month intervals and all except Company A maintaining in-house internal interconnect solutions. To reinforce the compounding dynamics, the results of all four companies are presented below:
The dramatic drop off in profitability that Company C and D experience is attributed to their late entry into a market whereby most of the premium designs are already consumed by Company A and B, and correspondingly severe market gross margin erosion is putting enormous pressure on Company C and D operations to hold costs down, at a time when two of their main competitors thrive. The additional two data points are provided to highlight that relative small additional delays (6 month delay for Company C relative to Company A), have dramatic effects on success in highly competitive markets.
Basic economic principles were used to show that given that high complexity interconnect solutions are required to meet the needs of SoCs in the convergence era that it is more economical to buy them rather than make them. The assumptions made in this paper are conservative given that convergence is accelerating, forcing even more challenging requirements over time that make complexity at the chip level grow exponentially.
For brevity, this paper did not address the effects of competition beyond the first two companies in the product category, other than anecdotally introducing Company C and Company D to show how rapidly the profit potential of a highly competitive market can erode.
Additionally, only 1 product development scenario was discussed in the paper. However, the conclusions made are consistent with the semiconductor industry trend showing that utilizing third party IP has become more economical than internally designing and maintaining an equivalent.
This paper represents the state of the semiconductor industry today. Winning and losing in competitive markets are often established in the early months of a new segment’s emergence that often commoditize rapidly. Since the business of engineering complex SoCs is much more complex than it was in the past, the decisions that determine a company’s potential competitive advantage (and thus it’s ability to win) must now be anchored in sound economic decisions as well as having clear technical merits.
By “normalizing” the technical merits between the solutions (assuming that both companies in the example eventually realized similar products) this paper highlights the vital importance of the economic component in the decision making process. And as the internal interconnect rapidly becomes the most critical architecture component in the SoC design process, the risks related to internal interconnect design and verification are moving rapidly toward the dominating aspect of the SoC design.
For complex SoCs, it is no longer economical to maintain in house internal interconnect architectures, because they now require an additional level of intelligent services to be engineered and maintained, in addition to the bus features, in order to meet end requirements. Third party intelligent internal interconnects represents a dramatically lower risk alternative that can mean the difference between winning and losing.