| Mixed-signal verification lies at the heart of a designer's constant battle between silicon accuracy and shorter development time. |
Silicon accuracy, essential to meeting performance parameters, is typically achieved in the design process by detailed transistor-level simulation or bottom-up design using a Spice-based simulator. For analog and mixed-signal designers forced to accurately characterize the performance and behavior of increasingly complex and sensitive circuits, this methodology has been essential to their success.
To minimize time to tape-out, however, there's a need for an accelerated design flow that maximizes parallel efforts and uses abstractions of the blocks to complete chip simulation and verification. Typically, designers need to use a top-down methodology with a heavy emphasis on behavioral modeling to achieve this goal.
Over the past decade, digital engineers have dramatically shortened the development cycle using a top-down approach. But as designers integrate increasingly larger amounts of analog and mixed-signal circuitry on-chip, abstracting, verifying, and automating the verification of these portions of the design process inhibits rapid IC development.
Recently, a design team from Freescale Semiconductor set out to tackle these disparate priorities in digital and mixed-signal design. The project centered around the design of a next generation power management and user interface (PMUI) IC for portable applications.
The MC13890 is a PMUI product providing general power supply, battery interface, speaker, handset, alert and microphone audio, DAC, ADC and CODECs, USB connectivity, logic control, and backlight and fun lighting driver functions. The chip is targeted for the GSM/GPRS/EDGE handset market for architectures that do not use a separate applications processor. It is, however, protocol independent and may fit other applications due to its modular functionality.
Figure 1 — Block diagram of audio-with-power management IC
Historically, as in many mixed-signal designs, the sections of our team working on the digital and analog portions of our chips used highly differentiated design methodologies. Engineers crafting the digital control functions on the chip took advantage of the many advances in digital IC tools to rapidly build and simulate their designs from the top down. For functional verification they used a mix of Cadence Design Systems' Verilog-XL and NC-Verilog, and Synopsys' VCS simulators.
Engineers designing the analog functions of the chip, on the other hand, historically employed a bottom-up, circuit-based, transistor-level methodology. Analog module verifications were run using an internal Spice based simulator. When a design required modules with higher levels of complexity, we often could only run basic power-up simulations in this old methodology.
Over the past few years, in an effort to increase our capacity and speed up simulation, we included FastMOS simulation in our design flow. However, it was not truly integrated and required some difficult script maintenance. Simulations therefore took a long time to complete. Using this methodology was sufficient in earlier, less complex designs to generate good test coverage. Even with FastMOS in the flow, however, we still faced a daunting simulation challenge at the top level when we designed complex parts with a large number of blocks, subsystems and a high device count.
In January 2004, we sat down with engineers from Cadence to find ways to accelerate the design flow. Our lead verification engineer wanted to gain more visibility into the verification process by creating a test bench and verification cycle for analog and mixed-signal circuits similar to the top-down methodology used by our designers building the digital functions on the chip. Our goal was to move away from troubleshooting analog designs which used the traditional, time-consuming methodology of probing on nets and visually inspecting waveforms.
We hoped to accomplish that task by moving our analog engineers into a methodology where they would create both behavioral models and transistor-level designs and then check the functionality of one against the other. Ultimately, we desired to create an environment where we could run large mixed-level simulations of the entire design.
Our team moved quickly to adopt and integrate a top-down, mixed-signal and mixed-level design methodology into our established bottom-up approach. Since many modules in this particular chip design drew on legacy IP, we relied heavily on pre-existing and proven data. We still faced the difficult challenge of creating behavioral models without delaying our development schedule. To accomplish this task, we began migrating those engineers who used our internal Spice simulator at the module level to the Virtuoso Spectre Circuit Simulator and the Virtuoso UltraSim full-chip Simulator. This gave us plug-and-play compatibility with Virtuoso Spectre format netlists and models.
We decided to use Virtuoso AMS Designer to integrate a top-down approach into the flow. This new platform supports "meet-in-the-middle" design methodologies by treating schematic editor blocks and textual descriptions equally, and by accepting descriptions in a wide range of standard language formats, including VHDL, VHDL-AMS, Verilog, Verilog-AMS, Spice, FastSpice and parasitics.
The first goal in any top down design methodology is to simulate the design at the top level with only behavioral models. Typically this is done before any transistor level design work has begun.
In this project designers used the detailed design specification to create Verilog-AMS behavioral models and test benches to check the model behavior. By creating Verilog-AMS models that mirror the design spec, the engineers essentially created a golden version of the design that exists in behavioral code, a simulatable goal to strive for in performance when later creating the transistor level design.
The design engineers also used Verilog-AMS in the test benches to more accurately represent real-world stimulus and environment. The same test benches could then be used later on in the design process to verify the transistor level designs. As the design progressed, behavioral models could be improved or enhanced to reflect true transistor circuit performance.
One of the key advantages of this approach was the ability it gave designers to use multiple models of a block in the design. Different models could be used to verify different performance characteristics of driving blocks in the design. Designers could simply swap out blocks using a hierarchy editor. Moreover, designers could swap out a behavioral model for a transistor level circuit without making changes to the actual design.
This flexibility permitted our designers to work at different levels of abstraction. They were able to combine Verilog-AMS or behavioral models with schematic representations, and easily move from full behavioral to transistor-level descriptions without editing or changing a test bench or schematic.
They could save a particular design configuration with any combination of behavioral models and transistor level representations of different blocks. By saving multiple configurations of a design, a design engineer could verify certain attributes, specifications, or performance of the design.
One of the key bottlenecks we faced in older methodologies was the limited configurability of the interface elements. In addition, they did not support bi-directional ports. As a result, anytime we wanted to introduce that capability into our circuit simulation, we had to go through the time-consuming process of manually modifying each module.
With our new design environment we can automatically insert interface elements (IEs) to translate signals from one domain to the next. This allows us to easily experiment with different configurations and trade simulation speed for accuracy.
Most importantly, since IEs are written in standard Verilog-AMS, they are completely configurable and can automatically embed bi-directional and supply sensitive features. If we need one interface to support a 1.8-V supply and a second to support a 3.3-V supply, the platform automatically programs each element for the appropriate threshold voltage.
Whether we're using a top-down or bottom-up approach, this new approach allows us to quickly compare results, experiment with our designs and find new efficiencies. Moreover, by allowing us to work at multiple abstraction levels in a single environment, we can now target detailed design at only those points needed for a given test. The environment also allows us to leverage top-level information for block design and, subsequently, the re-verification of blocks in their top-level context.
Top level test coverage
Once we successfully moved to a mixed top-down/bottom-up methodology, our design team received first past silicon and was able to distribute it to our customers to expedite their development cycles. One key to that achievement was our team's ability to log several thousand mixed-signal and mixed-level functional tests on the design.
During the process, the engineers verifying top-level mixed signal circuits saw test coverage improve. Moreover, they expect to achieve further efficiencies using this same top down, bottom up, mixed-signal, mixed-level design methodology on future projects.
Our new mixed-signal design environment allows us to create functional verification configurations on the fly. We can choose which modules will be simulated at the digital level, which modules at the analog behavioral level, and which module simulation will remain at the transistor level.
This ability to capture the full-chip specification offers us tremendous advantages in terms of testing out new architectures and accelerating verification. It also provides better insight into why tests are failing. Since simulation run times are now shorter, we can run more tests and gain higher coverage on the analog and mixed-signal portions than ever before.
One of the major accomplishments of this project was our ability to create self-checking test benches at the behavioral level for the analog/mixed-signal functions. By capturing test specifications in Verilog-AMS and running simple go/no-go tests during simulation, we are now able to eliminate the time-consuming task of checking waveforms to ensure design functionality.
Another key advantage we gained from this project was the simplified development of reusable intellectual property (IP). Since our new design environment supports all major industry standard languages, every time we develop a new block in Verilog-AMS, we can now reuse that behavioral IP across the entire power management group. By simplifying that process, we plan to accelerate future designs and further improve our productivity.
Of course, some issues still need to be ironed out. Our limited familiarity with the tools made some tasks difficult. The limitation of not being able to use out-of-module references with relation to current impacted our productivity in power simulations. However, this has recently been addressed in the latest version of Virtuoso AMS Designer and we are anxious to test this out on our latest design project.
As analog and mixed-signal verification plays an increasingly important role in ICs for power management in portable applications, we are constantly searching for new and more efficient ways to design and verify these functions within the scope of the total chip design. By moving to a simulation environment which allows us to combine our existing bottom-up, analog-centric methodology with a top-down, digital-centric design and verification methodology, we have enhanced our ability to debug and verify our mixed-signal designs while shortening our development cycles.
Mike Metroka is Global Power Management Development Manager at Freescale Semiconductor Inc.
Felicia James is Vice President and General Manager of Virtuoso Platform Products at Cadence Design Systems Inc.