Physical-layer circuits used for Serial Advanced Technology Attachment, PCI Express and other high-speed serial interfaces involve a combination of analog subblocks as well as logic-domain subblocks. PHY design teams are typically divided into groups of digital designers using digital design tools and analog designers who use analog (Spice-like) simulation tools.
A frequently overlooked aspect of this design dichotomy is that ownership of the digital-analog interface may be ambiguous or, worse yet, left unassigned. Digital-to-analog signals that are defined early on in the architecture phase may be inadvertently changed later. Examples are timing margins that are improperly specified or even logic signals that later change functionality or get inverted. The best "ounce of prevention" to avoid an expensive "pound of cure" later is a consistent methodology that tests this analog-digital "chasm."
Testing should include two categories: functional checks and timing-related checks.
Functional checks determine whether data is logically correct. They see, for example, that traffic flows from the most upstream digital portion of the transmitter through a channel "looped back" to the receiver all the way to appear at the output of the receiver's farthest downstream digital block without interruption or error.
Timing-related checks determine whether setup/hold margins and jitter margins are met to ensure that data is reliably passed through all parts of the data stream with sufficient margin over process, voltage and temperature.
Functional checks involve implementation of behavioral models for analog blocks to be able to run all of the test suites required for complete functional test coverage through HDL-type simulators.
Timing-related tests involve fewer simulations with high accuracy where simulation times are relatively long. To be believable, timing-related tests need accurate Spice models. Behavioral models with mixed-mode simulators allow simultaneous verification of the analog blocks with at least the first few surrounding stages of digital blocks for ensuring test coverage of the digital/analog boundary.
It is therefore critical to have a consistent methodology for avoiding this often-overlooked and mistake-prone link in the design chain. Also keep in mind:
- Create behavioral models for your analog blocks (PLL, CML buffer, CDR buffer and receiver).
- Maintain a dialog between analog and digital designers.
- Use chip debug to critically check and improve Spice models.
Drew Plant (firstname.lastname@example.org), director of technology at Knowlent Corp. (Santa Clara, Calif.)