How Verilog-AMS accelerates transistor modeling

But each new generation of semiconductor processing produces devices that don't quite behave the same as the last generation. New equations are needed to describe gate leakage current, pocket-implant effects, drain-induced barrier lowering, trap-assisted tunneling, and so forth. Analog simulators are not keeping up with the rapid pace of development, but Verilog-AMS promises a solution.

In the early days of circuit simulation, many semiconductor companies had a custom copy of the source code for Spice, derived from the FORTRAN source code from the University of California, Berkeley. These companies developed their own transistor compact models, improving upon the standard models that were part of Spice in order to give their designers an edge or to better model the devices in their own proprietary manufacturing processes.

Fast forward to the present. Commercial simulators from EDA companies have increased functionality and better performance than Berkeley Spice. Semiconductor companies have changed: some make money by designing chips and some (foundries) by manufacturing chips for other companies. But how does transistor modeling get done?

Foundries are faced with a challenge: they need to improve upon the available models to accurately describe the devices in their most advanced processes. But the foundries don't develop their own circuit simulators, and their customers may use any of a number of commercial offerings. The foundries are then bound to the release schedules of the most commonly used commercial simulators, and they must allow some time after the release for the latest version to be installed by their customers.

Figure 1 — Steps to simulating a new physical effect in a silicon device.

Practically, this means a delay of six months to a year from when the foundry settles on a new model to its availability to customers. As a result, transistor models are lagging behind fabrication technology.

Foundries are struggling to compensate: making complicated subcircuits for gate leakage or well proximity effects, or adding proprietary enhancements to otherwise standard models, such as the STI stress equations added to some simulators' BSIM3 MOSFET model or trap-assisted tunneling added to BSIM4.

Semiconductor companies with their own proprietary manufacturing process have worse trouble, since they are more protective of the intellectual property in their transistor models, and they don't have the same clout with EDA vendors for having new equations implemented.

The EDA vendors can't be happy with the status quo, either. They have to implement the various models and enhancements just to keep up with their competitors and satisfy their customers. The implementation of compact models is grunt work with no room for innovation, but the vendors need good programmers to make sure the work is done right because a poor implementation is a guarantee of performance problems.

So what's the solution? It lies with Verilog-AMS, the analog and mixed signal extensions to IEEE 1364 Verilog Hardware Description Language. Accellera, the electronics industry organization focused on EDA standards, approved Verilog-AMS 2.2 last November, and simulators are beginning to support the extensions introduced in that revision to better accomodate device models.

The Verilog-AMS standard defines an analog-only subset, Verilog-A, for use in analog circuit simulators. Accellera is currently working on SystemVerilog-AMS, which will provide designers a comprehensive language for analog and digital design and verification.

Using Verilog-A, foundries — as well as smaller semiconductor companies and university researchers — can implement their own model equations. Designers don't need to wait for a new version of the simulator; these new models are compiled on the fly and run with only a marginal decrease in performance compared with built-in models.

Verilog-A removes much of the tedium of compact model development. For example, the simulator computes the partial derivatives that must be computed by hand for compact models written in C. Figure 3 shows that Verilog-A can dramatically decrease the total number of lines of code that the model developer must write to describe a transistor model like BSIM3.

These models will run in any type of analog simulator: traditional Spice-like analog simulators, RF simulators, fast-Spice simulators, and parameter extraction tools. There is at least one commercial tool in each of these categories that supports Verilog-A. A number of mixed-mode simulators support the full Verilog-AMS standard.

Figure 3 — Comparison of the number of lines of source code.

Verilog-A is already in use at many semiconductor companies, and Verilog-A support is fast becoming a requirement for commercial as well as internal analog circuit simulators. At Analog Devices, I used Verilog-A to add self-heating to the BSIM3 MOSFET model in two days in order to improve modeling of high-voltage MOS devices in a proprietary high-voltage BiCMOS process at ADI; the research group at Berkeley that originally developed BSIM3 estimated it would take them six months to add this feature to the C code they distribute for the standard model.

The EIA Group's Compact Model Council is evaluating candidates for a next-generation MOSFET model. All five model development teams — from Berkeley's BSIM5 to the Penn State University/Philips Semiconductor "PSP" collaboration, as well as the EKV and HiSIM models — promised to deliver Verilog-A versions of their models for evaluation. Companies with Verilog-A support won't have to wait for implementation in a specific simulator.

Model developers will have better control over their intellectual property and yet have easier access to a wider range of potential customers. EDA vendors can refocus on adding simulation capabilities. Circuit designers will get new models faster. Verilog-A truly represents the future of transistor-level device modeling.

Geoffrey Coram is a staff CAD engineer at Analog Devices and served as chairman of the Accellera Verilog-AMS subcommittee for compact modeling. He can be reached at gjcoram@eda.org.