by Paul Lister, Mike Bassett, Phil Watten, Vincenzo Trignano, University of SussexBrighton, United KingdomAbstract
This paper outlines the virtual prototyping methodology originally developed to help define and implement handheld RF based embedded systems. The methodology has been developed to address the need to use appropriate languages and technologies for each task in hand and to deal with the interaction of these technologies. Real-time interaction has also been a key driver of this work whilst attempting not to limit the vertical reuse potential of the results. Another concern is protection and provision of intellectual property within an electronic model to encourage the distribution of models for easy evaluation. Finally, a description will be provided of a platform developed for lower complexity RF based devices with an example application developed within the VIPERS  project. Introduction
Virtual prototyping has been used in several forms to increase the early confidence in product design or function [2,3,4] and for a myriad of other reasons  as illustrated in Fig 1. Fig 1 - Stakeholders in virtual prototyping
This paper also gives an outline of the VIPERS platform RF macrocells and associated base band digital IP, the methodology described has been developed with reuse of this platform in mind. VIPERS virtual prototyping methodology
It is expected that a prospective user will start with either a written specification or a UML description of how the prototype should behave, along with some ideas on look and feel of the item, as well as maybe some pointers on the user interaction possibilities. The methodology reflects the division between and interaction of the two parallel development tracks, a graphical interactive virtual prototype model and a digital or system model to encapsulate the functionality.
This paper also presents an IDE (Interactive Development Environment) written to enable the rapid building of the virtual graphical prototype models [10,11]. Previous work [8, 12] has suggested that SystemC is a reasonable choice on which to base functional descriptions. One of the key reasons is that SystemC models can be targeted at both hardware and software tool chains. There are several available commercial SystemC tools [7,17] however we have chosen the open source SystemC simulator and libraries version 2.0.1 , this offers tool vendor independence and a cheaper solution for end users. It is also our impression from relevant conferences and discussion with users that a large percentage of SystemC users are using the freely available tools at this time.
Once the system behaviour and an associated test environment are captured in SystemC, it is possible to reuse this environment throughout the system implementation work as a reference test platform. As components of the system are implemented in RTL SystemC, HDL or software they can still be co-simulated with the original SystemC testbench so achieving a significant amount of vertical testbench reuse.
Fig 2 illustrates the flow from candidate solutions through parallel development of the graphical virtual prototype and the SystemC functional model. With care it is possible that the functional and graphical model of the system be created in as independent object-oriented a fashion as possible to facilitate several candidate solutions for each. We will start by describing the graphical model creation and animation and then look at the SystemC electronic model aspect. Fig 2 - Simplified virtual prototyping methodology
An example simple design used several times in the development of this methodology is a hypothetical remote control that is being considered as a domestic product by a commercial partner as illustrated in Fig 3. The graphical virtual prototyping environment, as illustrated in Fig 4, allows a design to be built from enclosure, screen and button objects amongst others to form a high quality photo-realistic image as expanded in Fig 3, this is not a photograph!
The IDE operates in either design mode, where a new or existing device can be built and edited or it can be in run mode where the model is made interactive and responsive to messages between the functional model and the IDE. It also possible to make direct changes to the graphical model state during run time to assist in debugging.
Fig 3 – Graphical virtual prototype
The SystemC development environment chosen was Microsoft Visual Studio .NET 2003. This is a modern object oriented development environment, but this choice caused problems as will be discussed later. Since devices will often be based on existing designs and IP, it is necessary to support co-simulation with VHDL blocks, which has already been verified and emulation/hardware interaction support, which is currently under development.
The two virtual model development threads are connected by a TCP-IP based communications protocol based on XML we have called LCCS - Logical Communications Control Service . This service is run on each machine that forms part of the overall system simulation to facilitate connectivity. Fig 4 – Virtual prototype IDE
The use of TCP/IP for LCCS allows the simulation components including the graphical virtual prototype, SystemC and HDL simulations to run on different machines and even platforms and communicate using local networks or the internet. This final point offers some security for IP developers in that the executable electronics model can be hosted on the internet and offered remotely to customers, although care needs to be taken over the granularity and scale of the data transfer performance or even real-time responsiveness is a driver . Also the executable portion of the model can be provided to the customer as a precompiled component which is difficult to reverse engineer.
The user of this approach has the choice to refine to and develop a custom SystemC solution for the system behaviour, but this paper follows the route through using the platform provided to accelerate the development. The most simple VIPERS platform being examined in this paper is shown in Fig 5. The SystemC model contains the RF macrocell as a digital part only, although a demonstration board is available that provides the full platform including the analogue RF parts. It should be noted that VIPERS IP blocks are available separately from the platform package.
Fig 5 – VIPERS RF based platform example
The architecture of the VIPERS platform makes it sensible to use a CPU to program the RF core, the user of the platform can take advantage of this core when deciding the prototype architecture, but this is less important during early design stages as illustrated in Fig 6, no commitment has been made to hardware or software tradeoffs. An example of this is the button de-bounce, this might be carried out by timers or software within a CPU core or by separate hardware components. Fig 6 - High level electronics model
The user can implement the refined architecture in a SystemC model to reflect the platform architecture, a possible trade-off is illustrated in Fig 7. Fig 7 - Refined core based implementation
The SystemC simulation is elaborated within a windows dynamic linked library which wraps the OSCI SystemC kernel within a container that adapts the interface to fit into a Microsoft windows .NET MFC programming environment. At run time this wrapper creates message queues that route messages to and from the graphical virtual prototype to signals exported from the SystemC model, as illustrated in Fig 8. The original open source SystemC libraries  have been treated as an object and not altered. Changes have often been made by others to achieve connectivity but at the cost of portability with new versions of the open source library, also there is a risk of breaking the open source library when making changes. Fig 8 - The overall SystemC simulation environment
This “platform friendly” model is ideally automatically translated into candidate C++ classes that can be used directly within the SystemC environment as illustrated in Fig 2. In most cases at present the translation will be manual and likely increase the risk of errors of interpretation and translation.
Experiments carried out using the described environment have confirmed that with a modest single computer it is possible to achieve real-time responsiveness between graphical models and the SystemC functional models. VHDL co-simulation has proven technically possible but problematic, this is due to the low RTL level nature of the models being simulated, and this has been improved by executing the VHDL simulation on a separate dedicated machine. The proposed solution for co-simulation with existing RTL VHDL is to place this in an FPGA or use existing silicon implementations where possible to accelerate overall system simulation performance. Concurrent & Future work
The research continues with more complex system examples, where often the interface to the user remains as simple and elegant as possible, but the complexity of the electronics contained becomes difficult to model, even at abstract levels, in real-time. The solutions being explored include distributed simulation, greater use of emulators with multiple processors and integration with existing hardware implementations of system blocks. One experiment we are carrying out is the use of an ARM processor and associated bus structures combined with a real-time operating system.
One of the directions that would increase the practicality of the VIPERS platform is the provision of cheap and easily available hardware emulation. The basic building blocks of a RF based component and complete systems are currently being put together within an FPGA to accelerate the simulation of the virtual prototype. An end user should be able to take the VIPERS platform, target an emulator board with a working example system that is similar to their needs, make changes and run these initially on the SystemC simulator and easily move these to the FPGA based emulator. A key driver to this activity is to provide emulation combined with the flexibility to change the platform hardware whilst keeping entry costs very low. It is expected the use of a commercially available FPGA evaluation board in the range of $99 to $199 should provide adequate resources for simple experiments.
UML has been explored to define the functional model , xUML  is being examined as a future proof route to define system behaviour and to treat SystemC as a implementation of the xUML that might be mapped automatically as machine language is currently compiled from C and C++. Conclusions
The virtual prototyping of products has many benefits for the early evaluation of a product idea and when this is combined with a SystemC platform model of the digital electronics, it forms a rapid experimental platform.
The methodology described in this paper uses SystemC as the cornerstone of system behaviour capture, this environment offers automated routes to both hardware and as the tools mature software implementations.
As the methodology evolves to include low cost emulation methods for the functional model combined with computer generated graphical models of the prototype, this will provide an economical and rapid development environment for new products.Acknowledgements
This work was funded as part of the ESPRIT framework 5 VIPERS project IST-2000-30023. We are grateful to our project colleagues for their constructive interaction, particularly Javier Mendigutxia of IKERLAN SA. The cooperation of our colleagues Teresa Riesgo and Eduardo de la Torre of Universidad Politécnica de Madrid and Sabastian Pantoja of Celestica Valencia is acknowledged.References
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