| First it was single ended drivers, then differential pairs, and now adaptive drivers and receivers are used to coax data down copper interconnects as fast as possible. Leading edge buffer technologies are forcing engineers to rethink their verification methodologies as the use of devices, which include advanced buffers displaying adaptive behaviors, have risen into the spotlight and also into frequent use. |
Many of these advanced buffers may be described as serdes (serialization/deserialization) devices, which are high-speed serial interconnects that require adequate verification of designs to ensure correct functionality (see Figure 1). Signal Integrity (SI) analysis tools are moving with these buffer technologies to cope with the task of adequately qualifying designs that use these new devices.
Traditional design methodologies of analyzing a design with single ended drivers that looked for overshoot, monotonic and ringing are becoming inefficient for these buffer technologies. Designers are performing longer simulations to evaluate the quality of “eye diagrams” not an easy task when the traditional approach has been to use Spice simulations of these complex buffers and accept the long simulation times (in the order of tens of minutes to hours for some simulations) for the “accuracy” that was afforded by this method.
Figure 1 Designing across the spectrum
With many backplane and intra-board connections now using serdes type devices, this long simulation time, which was once tolerated for a handful of nets, is now proving to be a limiting factor in qualifying an entire bus of the high-speed serdes devices that are now common in many designs.
Getting more information down the same copper
“I feel the need, the need for speed,” words made popular by the film Top Gun in 1986, are also a driving force in hardware design. Not precisely speed, though, but bandwidth. The ability to transfer more information in a shorter amount of time has driven a number of innovations in bus architecture design.
Faster memory interfaces are probably one of the most visible signs of this need. System designers have taken the innovative technologies that were part of RAMBUS and DDR memory and extended them to interleaved memory architectures and extensions of DDR to DDR2 and DDR3 with reduced latency versions. A polarization in the market, as captured by a 2003 EETimes survey, is currently taking place (see Figure 2).
Figure 2 New design starts, EE Times 2003
Forgoing the problematic timing issues of very fast synchronous designs, many have opted to jump into the serdes design space, taking advantage of these very high-speed asynchronous serial devices. While the recent adoption of serdes may seem to have crept up on us, the techniques for verifying designs that typically have a mix of classic SI, timing and serdes devices are well established, and a progression that has been made over the last decade.
Figure 3 Bus architectures, parallel to serial
Many designers are familiar with the classical SI and timing problems associated with increasing clock frequency on single ended synchronous signals. Having decided that it would be nice to protect our more sensitive and precious signals, we began moving these to differential signaling.
This can be seen in memory interfaces that used differential clocks and also in the migration from PCI and PCI-X signaling. This progression continued until the entire bus consisted almost entirely of high-speed differential signals.
To go even faster, there was a fundamental change in the way busses were now being architected. Bi-directional busses are being replaced by a pair of much faster uni-directional busses.
Wanting to go even faster, designers have progressed to entirely serial bit streams (PCI-Express) with embedded clocking (see Figure 3). To achieve more throughput than its predecessors, these uni-directional differential serial busses, created with serdes devices, use a number of signaling techniques to achieve high speeds while maintaining acceptable signal quality.
While it was now conceivable that slower parallel busses could be replaced with a single serial differential channel (a uni-directional pair being called channel), it is becoming evident that like HyperTransport, multiple channels are being used in parallel to achieve the bus bandwidths craved by today’s applications. Two of the most common techniques for getting the most out of the copper interconnects are pre-emphasis for drivers, and equalization for receivers (see Figure 4).
Figure 4 Pre-emphasis and equalization: boosting the initial voltage level of each edge to compensate for high frequency loss.
Termed pre-emphasis, this technique drives at lower amplitudes for subsequent identical digits. Only the initial change in logic state sees the full height of the waveform in an effort to keep the signal as clean as possible when it is wrapped on itself to create an eye-diagram, a common technique for evaluating these high-speed serdes channels. While this is called pre-emphasis, this is often implemented as de-emphasis.
Another technique which is used at the receiver is to filter the signal in an effort to remove higher order harmonics from the signal before it is presented to the internal control logic which determines the value of the bit stream being pushed down this copper interconnect. These techniques contribute immensely to the extremely high speeds attainable by serdes devices.
Some devices even dynamically tune themselves during operation. The good majority of serdes devices rely on the design engineer to pre-set drivers and receivers for their specific application. It is this requirement that squarely places the burden of verifying the correct operation of the channel onto the design engineer.
Verification requires new thinking
There are many SI engineers that advocate analysis on only a select sampling of representative traces of a board design. While providing analysis of those selected few is good, analyzing the entire bus is better.
Why? As the signaling speeds have increased, and the voltage swings that are being pushed down copper traces have decreased, designers now find themselves in a predicament. Serdes buffers are fast, there is no questioning that, but they are often sensitive.
Intel, for their PCI-Express interface, recommends a maximum number of vias for each trace. Other standards have similar electrical and mechanical requirements. Mechanical routing rules can provide reasonable assurances for well behaved examples, but to really find out what the signal looks like, simulation is required.
Connectors, combined with long and lossy interconnect contribute to non-ideal signal conditions. These conditions require either conservative design rules, or signal integrity simulation.
The effect of using pre-emphasis for serdes drivers can readily be seen by creating eye-diagrams. An eye-diagram is simply a wrapping of a really long simulation waveform over itself where the larger the opening in the middle (the eye), the better the signal quality.
As can be seen in Figure 5, increasing the pre-emphasis has a dramatic effect on the eye opening. Many specifications define the dimensions of how open the eye needs to be for compliance with the standard. Called an eye mask, this specification is overlaid on the eye diagram to validate conformance.
Figure 5 Eye diagrams
Many signal integrity tools in use today are able to display an eye diagram from simulation results. Important to the creation of good eye diagrams is the use of pseudo-random bit streams when simulating these signals. Correlation to physical measurements requires the same bit pattern as is used on actual hardware.
Standard patterns like PRBS-5, PRBS-7, PRBS-23, PRBS-31, Fiber Channel RPAT, CRPAT, and others are very useful for this. While shorter patterns may be repeated, doing so provides little benefit you get the same results over again. However, this is not the case if there is jitter introduced into the bit stream.
Jitter, along with exercising all of the patterns that your driver or receiver is sensitive to, are important considerations when creating simulations for use as eye diagrams. Another vital consideration is being able to perform simulations on the entire bus, not just a single channel, in a “reasonable” time.
Signal integrity simulations usually include IBIS models to model the current and voltage driving characteristics of the components used on boards. IBIS v4.1 extends the ability to model components that exhibit complex behavior by providing the capability for including Spice or VHDL-AMS as part of the device description. Particularly of interest is the use of these languages for buffer definitions.
Models that use static, V-T (Voltage-Time) and V-I (Voltage-Current) tables provide an excellent description of static device behavior and have fast simulation times. IBIS models created from actual measured devices are representative of the device actually measured. Determining the true manufacturing corner that is actually measured for corner case type simulations becomes difficult.
However, these models are often a very good representation of actual device behavior. IBIS models of static devices may also be created from Spice models using Spice 2 IBIS. Beginning with IBIS v4.1, IBIS now has the ability to wrap external Spice and VHDL-AMS models to handle devices that exhibit more than just static behavior. Spice
Having been used for much of the last few decades, Spice provides a familiar language in which to describe buffers. Many IC designs still rely heavily on Spice for transistor level simulations of circuits.
Either encrypted or plain text, these models are becoming more prevalent as the rise of adaptive drivers and receivers enter the market place. Usually available through an NDA with the silicon vendor, these models, when encrypted, are most likely to contain the actual transistor design used in the actual device.
Often this is not the case due to a reluctance to let any representation of the true transistor configuration out of a company. Using pure Spice for simulations of signal integrity circuits can be tedious, so IBIS provides a convenient mechanism to make these models available for use in signal integrity simulation tools.
A disadvantage of using transistor level Spice models is the simulation time. While IBIS table models take about a second to run, many Spice models simulate in the tens of minutes. This longer simulation time greatly reduces an engineer’s productivity as they are waiting for simulations to complete. This is further exasperated when validation of an entire bus is required; tens of minutes suddenly becomes days when the simulation time is multiplied by the number of channels.
Typically used as a behavioral modeling solution for adaptive drivers and receivers in IBIS, VHDL-AMS offers a number of significant advantages over Spice buffers. As a hardware description language, with both digital logic and analog modeling, complex logic decisions can be easily and readily created to control the internal working of a complex model.
While IC designers must create logic from lots of transistors, describing that behavior in VHDL-AMS is a simple high-level task. The advantage of being able to describe complex logic at a high-level, as well as the inherent simulation speed of VHDL-AMS, results in the simulation of complex buffers at speeds closer to that of IBIS table models.
The Cadence Design Systems Allegro community website had a poll that queried users for their preferred behavioral modeling language. The results from this May 2005 poll showed that 50% of respondents preferred VHDL-AMS as a behavioral modeling approach. As an IEEE standard and an official language for use in IBIS v4.1, VHDL-AMS buffer models offer a robust non-proprietary standard that is well defined for modeling serdes devices.
Drivers with complex current driving schedules become a simple logic block with current driving capabilities. Complex receivers with advanced filtering become an elegant filter equation with the poles and zeros of the filter described in a VHDL-AMS equation. VHDL-AMS is able to easily describe these adaptive drivers and receivers, while providing simulation speeds comparable to IBIS table models.
Many backplanes are passive (mostly)
Systems of boards are used in many places. Backplanes, which are mostly passive, are generally used to connect these systems together. Also common are connections through Flex PCBs and other connection methods (see Figure 6). The common chip-to-chip connections that are made on a single board can be verified by standard SI analysis.
However, analyses of signals that go off board, or at the backplane, require a systems consideration. Signal degradation caused by signal integrity effects onboard, connectors, losses in the copper (which may be significant for high-speed signals) and signal integrity effects of backplanes all contribute to a signal which arrives at its destination at less than optimal quality. Rules of thumb or mechanical design rules are often ineffective for solving these systems.
Figure 7 Multiboard analysis is often required
IBIS EBD (Electrical Board Description) models may be used for system wide analysis. However, these models do not contain coupling information that is required for simulating noise or crosstalk. Advanced drivers may need to consider coupling and noise. A more cohesive multi-board solution is required for these systems, one that contains coupling information, and allows for the description of complex topologies.
For example, IBIS EBDs are unable to describe multiple parallel terminations on a single differential pair. Multi-board solutions such as Mentor Graphics ICX use the board design so that coupling information is preserved, providing a superior simulation environment for serdes and other high-speed design scenarios.
Design and verification of the busses in common use today requires a two-pronged approach. Traditional SI and timing verification are as important as they have ever been. Serdes devices, which are representing a larger number of interconnects in new designs, require just as exhaustive an analysis and verification as the rest of the board.
Characterization of signal loss is critical for each channel in the entire design, not just a sampling. Complete coverage of these complex buffers requires models that are accurate and which simulate quickly a dual requirement that is met by IBIS v4.1 using VHDL-AMS buffer models.
Additionally, boards are seldom used in isolation. Multi-board analysis of the entire system provides a look at the whole system. While IBIS EBD models provide a good solution for this, without coupling information, IBIS EBD models are of limited use for high-speed serdes busses that traverse the backplane of a design. Using a multi-board solution that connects the actual board designs together is much better.
Designing with serdes buffers does not have to be a frightening or daunting exercise. All that is required is a good SI simulation tool, models that are accurate and simulate quickly to characterize the entire problem, and a willingness to consult the advice of colleagues or other engineers when needed. Serdes devices are here for a while, so being comfortable with how to verify and analyze designs that contain them is a must as these become a staple in many designs, sooner rather than later.
Matthew Hogan is high-speed technical marketing engineer at Mentor Graphics Corp. He can be reached at firstname.lastname@example.org.